Datasheet

Datasheet, Volume 2 171
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Processor Integrated I/O (IIO) Configuration Registers
3.3.3.23 CIPINTRC—Coherent Interface Protocol Interrupt Control Register
10:8 RW 000b
DCA Lookup Table Entry 0
For a TPH/DCA request, this field specifies the target NodeID[2:0] when the
inverted Tag[2:0] is 0.
7:1 RV 0h Reserved
0RW0b
Enable TPH/DCA
When disabled, PrefetchHint will not be sent on the coherent interface.
0 = Disable TPH/DCA Prefetch Hints
1 = Enable TPH/DCA Prefetch Hints
Notes: This table is programmed by BIOS and this bit is set when the table is
valid
CIPINTRC
Bus: 0 Device: 5 Function: 0 Offset: 14C
Bit Attr
Reset
Value
Description
63:45 RV 0h Reserved
44 RW 1b A20M Detect
43 RW 1b INTR Detect
42 RW 0b SMI Detect
41 RW 0b INIT Detect
40 RW 0b NMI Detect
39:38 RV 0h Reserved
37 RW 0b FERR Invert
36 RW 1b A20M Invert
35 RW 0b INTR Invert
34 RW 0b SMI Invert
33 RW 0b Init Invert
32 RW 0b NMI Invert
31:26 RV 0h Reserved
25 RW 0b Disable INTx Route to PCH
24 RW 0b Route NMI to MCA
23:21 RV 0h Reserved
20 RW 0b A20M Mask
19 RV 0h Reserved
18 RW 0b SMI / MSI Enable
17 RW 0b Init MSI Enable
16 RW 0b NMI MSI Enable
15:14 RV 0h Reserved
13 RW-L 1b
FERR Mask
Note: Locked by RSPLCK
12 RW 1b A20M Mask
CIPDCASAD
Bus: 0 Device: 5 Function: 0 Offset: 148
Bit Attr
Reset
Value
Description