Datasheet
Datasheet, Volume 2 17
4.2.16.10CORRERRCNT_2—Corrected Error Count Register........................ 449
4.2.16.11CORRERRCNT_3—Corrected Error Count Register........................ 450
4.2.16.12CORRERRTHRSHLD_0—Corrected Error Threshold Register........... 450
4.2.16.13CORRERRTHRSHLD_1—Corrected Error Threshold Register........... 451
4.2.16.14CORRERRTHRSHLD_2—Corrected Error Threshold Register........... 451
4.2.16.15CORRERRTHRSHLD_3—Corrected Error Threshold Register........... 451
4.2.16.16CORRERRORSTATUS—Corrected Error Status Register................. 452
4.2.16.17LEAKY_BKT_2ND_CNTR_REG Register....................................... 453
4.2.16.18DEVTAG_CNTRL[0:7]—Device Tagging Control for Logical
Rank 0 Register...................................................................... 454
4.2.16.19IOSAV_CH_B0_B3_BW_SERR Register....................................... 455
4.2.16.20IOSAV_CH_B4_B7_BW_SERR Register....................................... 455
4.2.16.21IOSAV_CH_B8_BW_SERR Register............................................ 456
4.2.16.22IOSAV_CH_B0_B3_BW_MASK Register...................................... 456
4.2.16.23IOSAV_CH_B4_B7_BW_MASK Register...................................... 457
4.2.16.24IOSAV_CH_B8_BW_MASK Register ........................................... 457
4.2.16.25IOSAV_DQ_LFSR[0:2] Register................................................. 458
4.2.16.26IOSAV_DQ_LFSRSEED[0:2] Register ......................................... 458
4.2.16.27IOSAV_DQ_LFSR1 Register...................................................... 459
4.2.16.28IOSAV_DQ_LFSRSEED1 Register............................................... 459
4.2.16.29IOSAV_DQ_LFSR2 Register...................................................... 460
4.2.16.30IOSAV_DQ_LFSRSEED2 Register............................................... 460
4.2.16.31MCSCRAMBLECONFIG—Data Scrambler Configuration Register ..... 461
4.2.16.32MCSCRAMBLE_SEED_SEL Register............................................ 461
4.2.16.33RSP_FUNC_CRC_ERR_INJ_DEV0_XOR_MSK Register................... 462
4.2.16.34RSP_FUNC_CRC_ERR_INJ_DEV1_XOR_MSK Register................... 462
4.2.16.35RSP_FUNC_CRC_ERR_INJ_EXTRA Register................................. 463
4.2.16.36x4modesel—MDCP X4 Mode Select Register................................ 464
4.3 Processor Home Agent Registers ....................................................................... 465
4.3.1 CSR Register Maps ............................................................................... 465
4.3.2 Processor Home Agent Register.............................................................. 466
4.3.2.1 TMBAR—Thermal Memory Mapped Register Range Base............... 466
4.3.2.2 TAD[0:11]—Target Address Decode DRAM Rule Register.............. 466
4.3.2.3 HaCrdtCnt—Home Agent Credit Counter Register ........................ 467
4.3.2.4 HtBase—Home Track Base Selection Register ............................. 470
4.3.2.5 HABGFTune—HA BGF Tuning Register........................................ 471
4.4 Power Control Unit (PCU) Registers.................................................................... 472
4.4.1 CSR Register Maps ............................................................................... 472
4.4.2 PCU0 Registers .................................................................................... 476
4.4.2.1 MEM_TRML_ESTIMATION_CONFIG—Memory Thermal
Estimation Configuration Register ............................................. 476
4.4.2.2 MEM_TRML_ESTIMATION_CONFIG2—Memory Thermal
Estimation Configuration 2 Register........................................... 477
4.4.2.3 MEM_TRML_TEMPERATURE_REPORT Register ............................. 477
4.4.2.4 MEM_ACCUMULATED_BW_CH_[0:3]—
MEM_ACCUMULATED_BW_CH_0 Register................................... 478
4.4.2.5 PRIP_NRG_STTS—Primary Plane Energy Status Register .............. 478
4.4.2.6 PACKAGE_POWER_SKU—Package Power SKU Register................. 478
4.4.2.7 PACKAGE_POWER_SKU_UNIT—Package Power SKU Unit Register.. 479
4.4.2.8 PACKAGE_ENERGY_STATUS—Package Energy Status Register ...... 479
4.4.2.9 PLATFORM_ID—Platform ID Register ......................................... 480
4.4.2.10 PLATFORM_INFO—Platform Information Register......................... 480
4.4.2.11 PP0_Any_Thread_Activity—PP0_Any_Thread_Activity Register...... 481
4.4.2.12 PP0_Efficient_Cycles—Power Plane 0 Efficient Cycles Register ....... 481
4.4.2.13 PP0_Thread_Activity—Power Plane 0 Thread Activity Register ....... 481
4.4.2.14 Package_Temperature Register................................................. 482
4.4.2.15 PP0_temperature Register........................................................ 482
4.4.2.16 PCU_REFERENCE_CLOCK—PCU Reference Clock Register ............. 482
4.4.2.17 P_STATE_LIMITS—P-State Limits Register.................................. 483
4.4.2.18 TEMPERATURE_TARGET—Temperature Target Register................ 484
4.4.2.19 TURBO_POWER_LIMIT—Turbo Power Limit Register..................... 484