Datasheet

Datasheet, Volume 2 169
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Processor Integrated I/O (IIO) Configuration Registers
11:9 RW 0h
RRB Size (Write Cache Size)
Specifies the number of entries used in each half of the write cache. The default is
to use all entries.
000 = 64 each side (128 total)
001 = 56 each side (112 total)
010 = 48 each side (96 total)
011 = 40 each side (80 total)
100 = 32 each side (64 total)
101 = 24 each side (48 total)
110 = 16 each side (32 total)
111 = 8 each side (16 total)
Used to limit performance for tuning purposes.
This size includes both isoch and non-isoch traffic.
8:6 RW 001b
Number of RTIDs for VCp
000 = 0
001 = 1
010 = 2
011 = 3
100 = 4
Others = Reserved
Limits the number of RTIDs used for VCp isoch. An equal number of RRB entries
are also reserved for VCp isoch. BIOS programs a value into this register based on
SKU.
5:3 RW 000b
Number of RTIDs for VC1
000 = 0
001 = 1
010 = 2
011 = 3
100 = 4
Others = Reserved
Limits the number of RTIDs used for VC1 isoch. An equal number of RRB entries
are also reserved for VC1 isoch. BIOS programs a value into this register based on
SKU.
2RW0b
Extended RTID Mode Enable
When this bit is set, NDR responses that IIO sends back on AK ring to Ubox or
Cbox and DRS responses it sends back on BL ring to Ubox or Cbox (and not to
Intel QPI), IIO copies DNID[2] on to the RHNID[2] field.
1RW0b
Disable write combining
Causes all writes to send a WB request as soon as M-state is acquired.
0 = Enable b2b Write Combining for writes from same port
1 = Disable b2b Write Combining for writes from same port
0RW0b
PCIRdCurrent/DRd.UC mode select
On Inbound Coherent Reads selection of RdCur or DRd is done based on this
configuration bit.
0 = PCIRdCurrent
1 = DRd.UC
CIPCTRL
Bus: 0 Device: 5 Function: 0 Offset: 140
Bit Attr
Reset
Value
Description