Datasheet

Processor Integrated I/O (IIO) Configuration Registers
168 Datasheet, Volume 2
3.3.3.19 GENPROTRANGE0_LIMIT—Generic Protected Memory Range 0 
Limit Address Register
3.3.3.20 CIPCTRL—Coherent Interface Protocol Control Register
GENPROTRANGE0_LIMIT
Bus: 0 Device: 5 Function: 0 Offset: 128
Bit Attr
Reset
Value
Description
63:51 RV 0h Reserved
50:16 RW-LB
000000
000h
Limit Address
This field indicates bits 50:16 of generic memory address range that needs to be
protected from inbound DMA accesses. The protected memory range can be
anywhere in the memory space addressable by the processor. Addresses that fall
in this range; that is, GenProtRange.Base[63:16]  Address [63:16] 
GenProtRange.Limit [63:16]) are completer aborted by IIO.
Setting the Protected range base address greater than the limit address disables
the protected memory region.
This range is orthogonal to Intel VT-d specification defined protected address
range. This register is programmed once at boot time and does not change after
that, including any quiesce flows. Since this register provides for a generic range,
it can be used to protect any system DRAM region from DMA accesses. The
expected usage for this range is to abort all PCIe accesses to the PCI-Segments
region.
15:0 RV 0h Reserved
CIPCTRL
Bus: 0 Device: 5 Function: 0 Offset: 140
Bit Attr
Reset
Value
Description
31 RW 0b
Flush Currently Pending Writes to DRAM from Write Cache
Whenever this bit is written to 1 (regardless what the current value of this bit is),
IRP block first clears bit 0 in CIPSTS register and takes a snapshot of the currently
pending write transactions to DRAM in Write Cache, wait for them to complete
fully (that is, deallocate the corresponding Write Cache/RRB entry) and then set
bit 0 in CIPSTS register.
30:29 RV 0h Reserved
28 RW 0b
Disable WriteUpdate Flow
When set, the PCIWriteUpdate command is never issued on IDI and the writes
that triggered this flow would be treated as ’normal’ writes and the rules
corresponding to the ’normal writes’ apply.
27:16 RV 0h Reserved
15 RW 1b Read Merge Enable
14:12 RW 0h
Socket ID
This is the BIOS programmed field that indicates the ’SocketID’ of this particular
socket. ’SocketID’ is the unique value that each socket in the system gets for
DCA/DIO target determination. Normally this value is the same as the
APICID[7:5] of the cores in the socket, but it can be other values as well, if
system topology were to not allow that straight mapping.
IIO uses strapped NodeID to compare against the target NodeID determined by
using the target SocketID value as a lookup into the CIPDCASAD register. If there
is a match, then a PCIDCAHint is not sent (since the data is already located in the
same LLC).
This register is not used for this comparison. It is not used by hardware at all.