Datasheet

Datasheet, Volume 2 167

Processor Integrated I/O (IIO) Configuration Registers
3.3.3.17 LMMIOH_LIMIT—Local MMIO High Base Register
3.3.3.18 GENPROTRANGE0_BASE—Generic Protected Memory Range 0 
Base Address Register
LMMIOH_LIMIT
Bus: N Device: 5 Function: 0 Offset: 118
Bit Attr
Reset
Value
Description
63:51 RV 0h Reserved
50:26 RW-LB
000000
0h
Local MMIOH Limit Address
This field corresponds to A[50:26] of MMIOH limit. An inbound memory address
that satisfies local MMIOH base [50:26]  A[63:26]  local MMIOH limit [50:26] is
treated as local a peer-to-peer transactions that does not cross the coherent
interface.
Notes:
1. Setting LMMIOH.BASE greater than LMMIOH.LIMIT disables local MMIOH
peer-to-peer.
2. This register is programmed once at boot time and does not change after
that, including any quiesce flows.
25:0 RV 0h Reserved
GENPROTRANGE0_BASE
Bus: 0 Device: 5 Function: 0 Offset: 120
Bit Attr
Reset
Value
Description
63:51 RV 0h Reserved
50:16 RW-LB
7FFFFFF
FFh
Base address
This field indicates bits 50:16 of generic memory address range that needs to be
protected from inbound DMA accesses. The protected memory range can be
anywhere in the memory space addressable by the processor. Addresses that fall
in this range; that is, GenProtRange.Base[63:16]  Address [63:16] 
GenProtRange.Limit [63:16]) are completer aborted by IIO.
Setting the Protected range base address greater than the limit address disables
the protected memory region. Note that this range is orthogonal to Intel VT-d
specification defined protected address range.
Since this register provides for a generic range, it can be used to protect any
system DRAM region or MMIO region from DMA accesses. But the expected usage
for this range is to abort all PCIe accesses to the PCI-Segments region.
15:0 RV 0h Reserved