Datasheet
Processor Integrated I/O (IIO) Configuration Registers
166 Datasheet, Volume 2
3.3.3.15 LMMIOL—Local MMIO Low Base Register
3.3.3.16 LMMIOH_BASE—Local MMIO High Base Register
LMMIOL
Bus: 0 Device: 5 Function: 0 Offset: 10C
Bit Attr
Reset
Value
Description
31:24 RW-LB 00h
Local MMIO Low Limit Address
This field corresponds to A[31:24] of MMIOL limit. An inbound memory address
that satisfies ’local MMIOL base[15:8] A[31:24] local MMIOL limit[15:8]’ is
treated as a local peer-to-peer transaction that does not cross the coherent
interface.
Notes:
1. Setting LMMIOL.BASE greater than LMMIOL.LIMIT disables local MMIOL peer-
to-peer.
2. This register is programmed once at boot time and does not change after
that, including any quiesce flows.
23:16 RV 0h Reserved
15:8 RW-LB 00h
Local MMIO Low Base Address
This field corresponds to A[31:24] of MMIOL base address. An inbound memory
address that satisfies ’local MMIOL base[15:8] A[31:24] local MMIOL
limit[15:8]’ is treated as a local peer-to-peer transaction that do not cross
coherent interface.
Notes:
1. Setting LMMIOL.BASE greater than LMMIOL.LIMIT disables local MMIOL peer-
to-peer.
2. This register is programmed once at boot time and does not change after
that, including any quiesce flows.
7:0 RV 0h Reserved
LMMIOH_BASE
Bus: N Device: 5 Function: 0 Offset: 110
Bit Attr
Reset
Value
Description
63:51 RV 0h Reserved
50:26 RW-LB
000000
0h
Local MMIOH Base Address
This field corresponds to A[50:26] of MMIOH base. An inbound memory address
that satisfies local MMIOH base [50:26] A[63:26] local MMIOH limit [50:26] is
treated as a local peer-to-peer transaction that does not cross the coherent
interface.
Notes:
1. Setting LMMIOH.BASE greater than LMMIOH.LIMIT disables local MMIOH
peer-to-peer.
2. This register is programmed once at boot time and does not change after
that, including any quiesce flows.
25:0 RV 0h Reserved