Datasheet

Datasheet, Volume 2 165

Processor Integrated I/O (IIO) Configuration Registers
3.3.3.13 MENCMEM_LIMIT—Intel
®
ME Non-coherent Memory Limit 
Address Register
3.3.3.14 CPUBUSNO—CPU Internal Bus Numbers Register
MENCMEM_LIMIT
Bus: 0 Device: 5 Function: 0 Offset: F8
Bit Attr
Reset
Value
Description
63:19 RW-LB
0000000
00000h
Intel ME UMA Limit Address
This field indicates the limit address which is aligned to a 1 MB boundary. Bits
[63:19] corresponds to A[63:19] address bits. Any address that falls within
MENCMEMBASE  Addr  MENCMEMLIMIT range is considered to target the UMA
range. Setting the MCNCMEMBASE greater than the MCNCMEMLIMIT disables this
range.
The range indicated by this register must fall within the low DRAM or high DRAM
memory regions as described using the corresponding base and limit registers.
18:0 RV 0h Reserved
CPUBUSNO
Bus: 0 Device: 5 Function: 0 Offset: 108
Bit Attr
Reset
Value
Description
31:17 RV 0h Reserved
16 RW-LB 0h
Valid
1 = IIO claims PCI config accesses from ring if:
— Bus # matches the value in bits 7:0 of this register and Device #  16
OR
— Bus # does not match either the value in bits 7:0 or 15:8 of this register
0 = IIO does not claim PCI config accesses from ring
15:8 RW-LB 00h
Internal bus number 1 of CPU Uncore
This field indicates the internal bus # of the rest of uncore. All devices are claimed
by UBOX on behalf of this component. Devices that do not exist within this
component on this bus number are master aborted by the UBOX.
7:0 RW-LB 00h
Internal bus number 0 of CPU Uncore
This field indicates the internal bus # of IIO and also PCH. Configuration requests
that target Devices 16-31 on this bus number must be forwarded to the PCH by
the IIO. Devices 0–15 on this bus number are claimed by the UBOX to send to IIO
internal registers. UBOX master aborts devices 8-15 automatically, since these
devices do not exist.