Datasheet

Processor Integrated I/O (IIO) Configuration Registers
164 Datasheet, Volume 2
3.3.3.10 NCMEM_BASE—NCMEM Base Register
3.3.3.11 NCMEM_LIMIT—NCMEM Limit Register
3.3.3.12 MENCMEM_BASE—Intel
®
Management Engine (Intel
®
ME) 
Non-coherent Memory Base Address Register
NCMEM_BASE
Bus: 0 Device: 5 Function: 0 Offset: E0
Bit Attr
Reset
Value
Description
63:26 RW-LB
3FFFFFF
FFFh
Non Coherent memory base address
This field describes the base address of a 64 MB aligned DRAM memory region on
Intel QPI that is non-coherent. Address bits 63:26 of an inbound address if it
satisfies ’NcMem.Base[63:26]  A[63:26]  NcMem.Limit[63:26]’ is considered to
be towards the non-coherent Intel QPI memory region. This means that IIO
cannot ever use ’allocating’ write commands for accesses to this region, over IDI.
This, in effect, means that DCA/TH writes cannot ever target this address region.
The range indicated by the Non-coherent memory base and limit registers does
not necessarily fall within the low DRAM or high DRAM memory regions as
described using the corresponding base and limit registers.
Usage Model for this range is ROL. Accesses to this range default to NSWr and
NSRd accesses on Intel QPI. But accesses to this range will use non-allocating
reads and writes, when enabled.
This register is programmed once at boot time and does not change after that,
including any quiesce flows.
25:0 RV 0h Reserved
NCMEM_LIMIT
Bus: 0 Device: 5 Function: 0 Offset: E8
Bit Attr
Reset
Value
Description
63:26 RW-LB
000000
0000h
Non Coherent memory limit address
Describes the limit address of a 64 MB aligned DRAM memory region on Intel QPI
that is non-coherent. Address bits 63:26 of an inbound address if it satisfies
’NcMem.Base[63:26]  A[63:26]  NcMem.Limit[63:26]’ is considered to be
towards the non-coherent Intel QPI memory region. This means that IIO cannot
ever use ’allocating’ write commands for accesses to this region, over IDI. This in
effect means that DCA/TH writes cannot ever target this address region.
The range indicated by the Non-coherent memory base and limit registers does
not necessarily fall within the low DRAM or high DRAM memory regions as
described using the corresponding base and limit registers.
This register is programmed once at boot time and does not change after that,
including any quiesce flows.
25:0 RV 0h Reserved
MENCMEM_BASE
Bus: 0 Device: 5 Function: 0 Offset: F0
Bit Attr
Reset
Value
Description
63:19 RW-LB
1FFFFFF
FFFFFh
Intel Management Engine (Intel ME) UMA Base Address
Indicates the base address which is aligned to a 1MB boundary. Bits 63:19
corresponds to A[63:19] address bits.
18:0 RV 0h Reserved