Datasheet

Datasheet, Volume 2 163
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Processor Integrated I/O (IIO) Configuration Registers
3.3.3.7 GENPROTRANGE2_LIMIT—Generic Protected Memory Range 2 
Limit Address Register
3.3.3.8 TOLM—Top of Low Memory Register
3.3.3.9 TOHM—Top of High Memory Register
GENPROTRANGE2_LIMIT
Bus: 0 Device: 5 Function: 0 Offset: C8
Bit Attr
Reset
Value
Description
63:51 RV 0h Reserved
50:16 RW-LB
000000
000h
Limit address
This field indicates bits 50:16 of the generic memory address range that needs to
be protected from inbound DMA accesses. The protected memory range can be
anywhere in the memory space addressable by the processor. Addresses that fall
in this range; that is, GenProtRange.Base[63:16]  Address [63:16] 
GenProtRange.
Limit [63:16] are completer aborted by IIO.Setting the Protected range base
address greater than the limit address disables the protected memory region.
This range is orthogonal to Intel VT-d specification defined protected address
range. This register is programmed once at boot time and does not change after
that, including any quiesce flows.
This region is expected to be used to protect against PAM region accesses
inbound, but could also be used for other purposes, if needed.
15:0 RV 0h Reserved
TOLM
Bus: 0 Device: 5 Function: 0 Offset: D0
Bit Attr
Reset
Value
Description
31:26 RW-LB 00h
TOLM address
This field indicates the top of low DRAM memory which is aligned to a 64 MB
boundary. A 32-bit transaction that satisfies ’0  Address[31:26]  TOLM[31:26]’
is a transaction towards main memory.
25:0 RV 0h Reserved
TOHM
Bus: 0 Device: 5 Function: 0 Offset: D4
Bit Attr
Reset
Value
Description
63:26 RW-LB
000000
0000h
TOHM address
This field indicates the limit of an aligned 64 MB granular region that decodes
>4 GB addresses towards system DRAM memory. A 64-bit transaction that
satisfies ’4G  A[63:26]  TOHM[63:26]’ is a transaction towards main memory.
This register is programmed once at boot time and does not change after that,
including during quiesce flows.
25:0 RV 0h Reserved