Datasheet

Processor Integrated I/O (IIO) Configuration Registers
162 Datasheet, Volume 2
3.3.3.5 GENPROTRANGE1_LIMIT—Generic Protected Memory Range 1 
Limit Address Register
3.3.3.6 GENPROTRANGE2_BASE—Generic Protected Memory Range 2 
Base Address Register
GENPROTRANGE1_LIMIT
Bus: 0 Device: 5 Function: 0 Offset: B8
Bit Attr
Reset
Value
Description
63:51 RV 0h Reserved
50:16 RW-LB
000000
000h
Limit address
This field indicates bits 50:16 of the generic memory address range that needs to
be protected from inbound DMA accesses. The protected memory range can be
anywhere in the memory space addressable by the processor. Addresses that fall
in this range; that is, GenProtRange.Base[63:16]  Address [63:16] 
GenProtRange.Limit [63:16]) are completer aborted by IIO.
Setting the Protected range base address greater than the limit address disables
the protected memory region.
This range is orthogonal to Intel VT-d specification defined protected address
range. This register is programmed once at boot time and does not change after
that, including any quiesce flows. Since this register provides for a generic range,
it can be used to protect any system DRAM region from DMA accesses. The
expected usage for this range is to abort all PCIe accesses to the PCI-Segments
region.
15:0 RV 0h Reserved
GENPROTRANGE2_BASE
Bus: 0 Device: 5 Function: 0 Offset: C0
Bit Attr
Reset
Value
Description
63:51 RV 0h Reserved
50:16 RW-LB
7FFFFFF
FFh
Base address
This field indicates bits 50:16 of the generic memory address range that needs to
be protected from inbound DMA accesses. The protected memory range can be
anywhere in the memory space addressable by the processor. Addresses that fall
in this range; that is, GenProtRange.Base[63:16]  Address [63:16] 
GenProtRange.Limit [63:16]) are completer aborted by IIO.
Setting the Protected range base address greater than the limit address disables
the protected memory region.
This range is orthogonal to Intel VT-d Specification defined protected address
range. This register is programmed once at boot time and does not change after
that, including any quiesce flows.
This region is expected to be used to protect against PAM region accesses
inbound, but could also be used for other purposes, if needed.
15:0 RV 0h Reserved