Datasheet

Datasheet, Volume 2 161
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Processor Integrated I/O (IIO) Configuration Registers
3.3.3.2 MMCFG—MMCFG Address Range Register
3.3.3.3 TSEG—TSeg Address Range Register
3.3.3.4 GENPROTRANGE1_BASE—Generic Protected Memory Range 1 
Base Address Register
MMCFG
Bus: 0 Device: 5 Function: 0 Offset: 84
Bit Attr
Reset
Value
Description
63:58 RW-LB 00h
MMCFG Limit Address
This field indicates the limit address which is aligned to a 64 MB boundary. Any
access that decodes to be between MMCFG.BASE  Addr  MMCFG.LIMIT targets
the MMCFG region and is aborted by IIO. Setting the MMCFG.BASE greater than
MMCFG.LIMIT disables this region.
57:32 RV 0h Reserved
31:26 RW-LB 3Fh
MMCFG Base Address
Indicates the base address which is aligned to a 64 MB boundary.
25:0 RV 0h Reserved
TSEG
Bus: 0 Device: 5 Function: 0 Offset: A8
Bit Attr
Reset
Value
Description
63:52 RW-LB 000h
TSeg Limit Address
This field indicates the limit address which is aligned to a 1 MB boundary. Bits 31:20
corresponds to A[31:20] address bits.Any access to falls within TSEG.BASE  Addr 
TSEG.LIMIT is considered to target the TSEG region and IIO aborts it. Setting the
TSEG.BASE greater than the limit disables this region.
51:32 RV 0h Reserved
31:20 RW-LB FE0h
TSeg Base Address
Indicates the base address which is aligned to a 1MB boundary. Bits 31:20
corresponds to A[31:20] address bits.
19:0 RV 0h Reserved
GENPROTRANGE1_BASE
Bus: 0 Device: 5 Function: 0 Offset: B0
Bit Attr
Reset
Value
Description
63:51 RV 0h Reserved
50:16 RW-LB
7FFFFFF
FFh
Base address
This field indicates bits 50:16 of the generic memory address range that needs to
be protected from inbound DMA accesses. The protected memory range can be
anywhere in the memory space addressable by the processor. Addresses that fall
in this range; that is, GenProtRange.Base[63:16]  Address [63:16] 
GenProtRange.Limit [63:16]) are completer aborted by IIO.
Setting the Protected range base address greater than the limit address disables
the protected memory region. Note that this range is orthogonal to Intel VT-d
specification defined protected address range.
Since this register provides for a generic range, it can be used to protect any
system DRAM region or MMIO region from DMA accesses. But the expected usage
for this range is to abort all PCIe accesses to the PCI-Segments region.
15:0 RV 0h Reserved