Datasheet

Processor Integrated I/O (IIO) Configuration Registers
160 Datasheet, Volume 2
3.3.2.15 PXPNXTPTR—PCI Express* Next Pointer Register
The PCI Express Capability List register enumerates the PCI Express Capability
structure in the PCI 3.0 configuration space.
3.3.2.16 PXPCAP—PCI Express* Capabilities Register
The PCI Express Capability List register enumerates the PCI Express Capability
structure in the PCI 3.0 configuration space.
3.3.3 Intel
®
VT-d, Address Mapping, System Management, 
Coherent Interface, Misc Registers
3.3.3.1 HDRTYPECTRL—PCI Header Type Control Register
PXPNXTPTR
Bus: 0 Device: 5 Function: 0,2 Offset: 41h
Bit Attr
Reset
Value
Description
7:0 RO E0h
Next Ptr
This field is set to the PCI PM capability
.
PXPCAP
Bus: 0 Device: 5 Function: 0, 2,4 Offset: 42h
Bit Attr
Reset
Value
Description
15:14 RV 0h Reserved
13:9 RO 00h Interrupt Message Number. Not applicable
8RO0bSlot Implemented. Not applicable
7:4 RO 1001b
Device/Port Type
This field identifies the type of device. It is set to for the DMA to indicate root
complex integrated endpoint device.
3:0 RO 2h
Capability Version
This field identifies the version of the PCI Express capability structure. Set to 2h
for PCI Express and DMA devices for compliance with the extended base registers.
HDRTYPECTRL
Bus: 0 Device: 5 Function: 0 Offset: 80
Bit Attr
Reset
Value
Description
31:3 RV 0h Reserved
2:0 RW 000b
Set Header Type to Single Function (clear MFD bit)
When set, function#0 with in the indicated device shows a value of 0 for bit 7 of
the HDR register, indicating a single function device. BIOS sets this bit, when only
function#0 is visible within the device, either because SKU reasons or BIOS has
hidden all functions but function#0 within the device using the DEVHIDE register.
Bit 0 is for Device 1
Bit 1 is for Device 2
Bit 3 is for Device 3
Currently this is defined only for devices 1, 2 and 3 because in other devices it is
expected that at least 2 functions are visible to the operating system or the entire
device is hidden.