Datasheet

16 Datasheet, Volume 2
4.2.14.2 TCRAP—Timing Constraints DDR3 Regular Access 
Parameter Register..................................................................419
4.2.14.3 TCRWP—Timing Constraints DDR3 Read Write Parameter 
Register.................................................................................420
4.2.14.4 TCOTHP—Timing Constraints DDR3 Other Timing 
Parameter Register..................................................................422
4.2.14.5 TCRFP—Timing Constraints DDR3 Refresh Parameter Register.......423
4.2.14.6 TCRFTP—Timing Constraints Refresh Timing Parameter Register....423
4.2.14.7 TCSRFTP—Timing Constraints Self-Refresh Timing 
Parameter Register..................................................................424
4.2.14.8 TCMR2SHADOW—Timing Constraints MR2 Shadow Timing 
Parameter Register..................................................................424
4.2.14.9 TCZQCAL—Timing Constraints ZQ Calibration Timing 
Parameter Register..................................................................425
4.2.14.10TCSTAGGER_REF Register........................................................426
4.2.14.11TCMR0SHADOW—MR0 Shadow Register.....................................426
4.2.14.12RPQAGE Register ....................................................................427
4.2.14.13IDLETIME—Page Policy and Timing Parameter Register.................427
4.2.14.14RDIMMTIMINGCNTL—RDIMM Timing Parameter Register ..............428
4.2.14.15RDIMMTIMINGCNTL2 Register...................................................429
4.2.14.16TCMRS—DDR3 MRS Timing Register ..........................................429
4.2.14.17RD_ODT_TBL0—Read ODT Lookup Table 0 Register.....................429
4.2.14.18RD_ODT_TBL1—Read ODT Lookup Table 1 Register.....................430
4.2.14.19RD_ODT_TBL2—Read ODT Lookup Table 2 Register.....................431
4.2.14.20WR_ODT_TBL0—Write ODT Lookup Table 0 Register....................432
4.2.14.21WR_ODT_TBL1—Write ODT Lookup Table 1 Register....................433
4.2.14.22WR_ODT_TBL2—Write ODT Lookup Table 2 Register....................434
4.2.14.23MC_INIT_STAT_C Register .......................................................434
4.2.14.24RSP_FUNC_MCCTRL_ERR_INJ Register.......................................435
4.2.14.25PWMM_STARV_CNTR_PRESCALER Register.................................435
4.2.14.26WDBWM—WDB Watermarks Register.........................................436
4.2.14.27WDAR_MODE Register .............................................................436
4.2.14.28SPARING Register ...................................................................437
4.2.15 Integrated Memory Controller DDR3 Training Registers..............................437
4.2.15.1 IOSAV_SPEC_CMD_ADDR_[0:3]—IOSAV Special Command 
ADDR Seq 0 Register...............................................................437
4.2.15.2 IOSAV_CH_ADDR_UPDT_[0:3]—IOSAV Channel Address 
Update Seq 0 Register .............................................................438
4.2.15.3 IOSAV_CH_ADDR_LFSR_[0:3]— IOSAV Channel Address 
LFSR Seq 0 Register ................................................................439
4.2.15.4 IOSAV_CH_SPCL_CMD_CTRL_[0:3]—IOSAV Channel Special
Command Control Seq 0 Register..............................................439
4.2.15.5 IOSAV_CH_SUBSEQ_CTRL_[0:3]—IOSAV Channel Sub-Sequence 
Control Seq 0 Register.............................................................440
4.2.15.6 IOSAV_CH_SEQ_CTRL—IOSAV Channel Sequence 
Control Register......................................................................441
4.2.15.7 IOSAV_CH_STAT—IOSAV Channel Status Register.......................442
4.2.15.8 IOSAV_CH_DATA_CNTL—IOSAV Channel Data 
Control Register......................................................................443
4.2.15.9 IOSAV_CH_DATA_CYC_MSK—IOSAV Channel Data Cycle 
Mask Register.........................................................................443
4.2.16 Integrated Memory Controller Error Registers...........................................444
4.2.16.1 ROUNDTRIP0—Round-Trip Latency Register................................444
4.2.16.2 ROUNDTRIP1—Round-Trip Latency 1 Register .............................444
4.2.16.3 IOLATENCY0—IO Latency Register.............................................445
4.2.16.4 IOLATENCY1—IO Latency 1 Register..........................................445
4.2.16.5 WDBPRELOADREG0—WDB Data Load Register 0..........................446
4.2.16.6 WDBPRELOADREG1—WDB Data Load Register 1..........................446
4.2.16.7 WDBPRELOADCTRL—WDB Preload Control Register......................447
4.2.16.8 CORRERRCNT_0—Corrected Error Count Register ........................448
4.2.16.9 CORRERRCNT_1—Corrected Error Count Register ........................449