Datasheet

Datasheet, Volume 2 159
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Processor Integrated I/O (IIO) Configuration Registers
3.3.2.11 CAPPTR—Capability Pointer Register
The CAPPTR provides the offset to the location of the first device capability in the
capability list.
3.3.2.12 INTL—Interrupt Line Register
The Interrupt Line register is used to communicate interrupt line routing information
between initialization code and the device driver
.
3.3.2.13 INTPIN—Interrupt Pin Register
3.3.2.14 PXPCAPID—PCI Express* Capability Identity Register
The PCI Express Capability List register enumerates the PCI Express Capability
structure in the PCI 3.0 configuration space.
CAPPTR
Bus: 0 Device: 5 Function: 0,2,4 Offset: 34h
Bit Attr Reset Value Description
7:0 RO
Dev 5, F 0,2
= 40h
Dev 5, F4
= 44h
Capability Pointer
Points to the first capability structure for the device which is the PCIe
capability
.
INTL
Bus: 0 Device: 5 Function: 0,2 Offset: 3Ch
Bit Attr
Reset
Value
Description
7:0 RO 00h
Interrupt Line
Not applicable for these devices
INTPIN
Bus: 0 Device: 5 Function: 0,2 Offset: 3Dh
Bit Attr
Reset
Value
Description
7:0 RO 00h
Interrupt Pin
Not applicable since these devices do not generate any interrupt on their own
PXPCAPID
Bus: 0 Device: 5 Function: 0, 2 Offset: 40h
Bit Attr
Reset
Value
Description
7:0 RO 10h
Capability ID
This field provides the PCI Express capability ID assigned by PCI-SIG
..