Datasheet

Datasheet, Volume 2 157
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Processor Integrated I/O (IIO) Configuration Registers
3.3.2.5 RID—Revision Identification Register
This register contains the revision number of the Integrated I/O.
3.3.2.6 CCR—Class Code Register
This register contains the Class Code for the device.
3.3.2.7 CLSR—Cacheline Size Register
RID
Bus: 0 Device: 5 Function: 0,2,4 Offset: 08h
Bit Attr
Reset
Value
Description
7:0 RO 00h
Revision_ID
Reflects the Uncore Revision ID after reset.
Reflects the Compatibility Revision ID after BIOS writes 69h to any RID register in any
processor function.
Implementation Note: Read and write requests from the host to any RID register in
any processor Intel QPI function are re-directed to the IIO cluster. Accesses to the
CCR field are also redirected due to DWord alignment. It is possible that JTAG
accesses are direct, so will not always be redirected.
CCR
Bus: 0 Device: 5 Function: 0,2,4 Offset: 09h
Bit Attr
Reset
Value
Description
23:16 RO 08h
Base Class
For almost all IIO device/functions this field is hardwired to 06h, indicating it is a
’Bridge Device’. Non-bridge generic devices use a value of 08h, indicating it is a
’Generic System Peripheral’.
15:8 RO 80h
Sub-Class
For almost all IIO device/functions, this field defaults to 00h indicating host bridge.
Non-bridge devices use a value of 80h.
7:0 RO 00h
Register-Level Programming Interface
Set to 00h for all non-APIC devices.
CLSR
Bus: 0 Device: 5 Function: 0,2,4 Offset: 0Ch
Bit Attr
Reset
Value
Description
7:0 RW 0h
Cacheline Size
This register is set as RW for compatibility reasons only. Cacheline size for the
processor is always 64B.