Datasheet

Processor Integrated I/O (IIO) Configuration Registers
156 Datasheet, Volume 2
3.3.2.4 PCISTS—PCI Status Register
The PCI Status register is a 16-bit status register that typically reports the occurrence
of various events associated with the primary side of the “virtual” PCI Express device.
Since these devices are host bridge devices, the only field that has meaning is
“Capabilities List.”
3RO0b
Special Cycle Enable
Not applicable. Hardwired to 0.
2RO0b
Bus Master Enable
Hardwired to 0 since these devices don’t generate any transactions
1RO0b
Memory Space Enable
Hardwired to 0 since these devices don’t decode any memory BARs
0RO0b
IO Space Enable
Hardwired to 0 since these devices don’t decode any IO BARs
PCICMD
Bus: 0 Device: 5 Function: 0,2,4 Offset: 04h
Bit Attr
Reset
Value
Description
PCISTS
Bus: 0 Device: 5 Function: 0,2,4 Offset: 06h
Bit Attr
Reset
Value
Description
15 RO 0b
Detected Parity Error
This bit is set when the device receives a packet on the primary side with an
uncorrectable data error (including a packet with poison bit set) or an
uncorrectable address/control parity error. The setting of this bit is regardless of
the Parity Error Response bit (PERRE) in the PCICMD register. R2PCIe will never
set this bit.
14 RO 0b
Signaled System Error
Hardwired to 0
13 RO 0b
Received Master Abort
Hardwired to 0
12 RO 0b
Received Target Abort
Hardwired to 0
11 RO 0b
Signaled Target Abort
Hardwired to 0
10:9 RO 0h
DEVSEL# Timing
Not applicable to PCI Express. Hardwired to 0.
8RO0b
Master Data Parity Error
Hardwired to 0
7RO0b
Fast Back-to-Back
Not applicable to PCI Express. Hardwired to 0.
6RV0hReserved
5RO0b
pci bus 66 MHz capable
Not applicable to PCI Express. Hardwired to 0.
4RO1b
Capabilities List
This bit indicates the presence of a capabilities list structure
3RO0b
INTx Status
Hardwired to 0
2:0 RV 0h Reserved