Datasheet

Datasheet, Volume 2 155
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Processor Integrated I/O (IIO) Configuration Registers
3.3.2 PCI Configuration Space Registers Common to Device 5
3.3.2.1 VID—Vendor Identification Register
3.3.2.2 DID—Device Identification Register
3.3.2.3 PCICMD—PCI Command Register
This register defines the PCI 3.0 compatible command register values applicable to PCI
Express space.
VID
Bus: 0 Device: 5 Function: 0,2,4, Offset: 00h
Bit Attr
Reset
Value
Description
15:0 RO 8086h
Vendor Identification Number
The value is assigned by PCI-SIG to Intel.
DID
Bus: 0 Device: 5 Function: 0,2,4 Offset: 02h
Bit Attr
Reset
Value
Description
15:0 RO 3C28h
Device Identification Number
Device ID values vary from function to function. Bits 15:8 are equal to 3Ch for the
processor. The following list is a breakdown of the function groups.
3C00h–3C1Fh : PCI Express and DMI ports
3C20h–3C3Fh : IO Features (APIC, VT)
3CA0h–3CBFh : Home Agent/Memory Controller
3CC0h–3CDFh : Power Management
3CE0h–3CFFh : Cbo/Ring
PCICMD
Bus: 0 Device: 5 Function: 0,2,4 Offset: 04h
Bit Attr
Reset
Value
Description
15:11 RV 0h Reserved
10 RO 0b
INTx Disable
Not applicable for these devices
9RO 0b
Fast Back-to-Back Enable
Not applicable to PCI Express and is hardwired to 0
8RO 0b
SERR Enable
This bit has no impact on error reporting from these devices
7RO 0b
IDSEL Stepping/Wait Cycle Control
Not applicable to internal devices. Hardwired to 0.
6RO 0b
Parity Error Response
This bit has no impact on error reporting from these devices
5RO 0b
VGA palette snoop Enable
Not applicable to internal devices. Hardwired to 0.
4RO 0b
Memory Write and Invalidate Enable
Not applicable to internal devices. Hardwired to 0.