Datasheet

Datasheet, Volume 2 15
4.2.12.29RIRILV2OFFSET_3—RIR Range Rank Interleave 2 
OFFSET Register..................................................................... 394
4.2.12.30RIRILV3OFFSET_3—RIR Range Rank Interleave 3 
OFFSET Register..................................................................... 395
4.2.12.31RIRILV4OFFSET_3—RIR Range Rank Interleave 4 
OFFSET Register..................................................................... 395
4.2.12.32RIRILV5OFFSET_3—RIR Range Rank Interleave 5 
OFFSET Register..................................................................... 396
4.2.12.33RIRILV6OFFSET_3—RIR Range Rank Interleave 6 
OFFSET Register..................................................................... 396
4.2.12.34RIRILV7OFFSET_3—RIR Range Rank Interleave 7 
OFFSET Register..................................................................... 397
4.2.12.35RIRILV0OFFSET_4—RIR Range Rank Interleave 0 
OFFSET Register..................................................................... 397
4.2.12.36RIRILV1OFFSET_4—RIR Range Rank Interleave 1 
OFFSET Register..................................................................... 398
4.2.12.37RIRILV2OFFSET_4—RIR Range Rank Interleave 2 
OFFSET Register..................................................................... 398
4.2.12.38RIRILV3OFFSET_4—RIR Range Rank Interleave 3 
OFFSET Register..................................................................... 399
4.2.12.39RIRILV4OFFSET_4—RIR Range Rank Interleave 4 
OFFSET Register..................................................................... 399
4.2.12.40RIRILV5OFFSET_4—RIR Range Rank Interleave 5 
OFFSET Register..................................................................... 400
4.2.12.41RIRILV6OFFSET_4—RIR Range Rank Interleave 6 
OFFSET Register..................................................................... 400
4.2.12.42RIRILV7OFFSET_4—RIR Range Rank Interleave 7 
OFFSET Register..................................................................... 401
4.2.12.43RSP_FUNC_ADDR_MATCH_LO Register...................................... 401
4.2.12.44RSP_FUNC_ADDR_MATCH_HI Register ...................................... 402
4.2.12.45RSP_FUNC_ADDR_MASK_LO Register........................................ 402
4.2.12.46RSP_FUNC_ADDR_MASK_HI Register ........................................ 403
4.2.13 Integrated Memory Controller Thermal Control Registers........................... 403
4.2.13.1 PXPCAP—PCI Express* Capability Register ................................. 403
4.2.13.2 ET_CFG—Electrical Throttling Configuration Register.................... 404
4.2.13.3 CHN_TEMP_CFG—Channel TEMP Configuration Register ............... 405
4.2.13.4 CHN_TEMP_STAT—Channel TEMP Status Register ....................... 405
4.2.13.5 DIMM_TEMP_OEM_[0:2]—DIMM TEMP Configuration Register....... 406
4.2.13.6 DIMM_TEMP_TH_[0:2]—DIMM TEMP Configuration Register ......... 407
4.2.13.7 DIMM_TEMP_THRT_LMT_[0:2]—DIMM TEMP 
Configuration Register............................................................. 408
4.2.13.8 DIMM_TEMP_EV_OFST_[0:2]—DIMM TEMP 
Configuration Register............................................................. 409
4.2.13.9 DIMMTEMPSTAT_[0:2]—DIMM TEMP Status Register ................... 410
4.2.13.10PM_CMD_PWR_[0:2]—Electrical Power and Thermal 
Throttling Command Power Register.......................................... 411
4.2.13.11ET_DIMM_AVG_SUM_[0:2]—Electrical Throttling Energy 
Accumulator Register .............................................................. 412
4.2.13.12ET_DIMM_TH_[0:2]—Electrical Throttling Energy 
Threshold Register.................................................................. 412
4.2.13.13THRT_PWR_DIMM_[0:2]—THRT_PWR_DIMM_0 Register .............. 413
4.2.13.14PM_PDWN—PM CKE OFF Control Register................................... 413
4.2.13.15MC_TERM_RNK_MSK—MC Termination Rank Mask Register.......... 415
4.2.13.16PM_SREF—PM Self-Refresh Control Register............................... 415
4.2.13.17PM_DLL—PM DLL Config Register.............................................. 416
4.2.13.18ET_CH_AVG—Electrical Throttling Energy Averager Register ......... 417
4.2.13.19ET_CH_SUM—Electrical Throttling Energy Accumulator Register .... 417
4.2.13.20ET_CH_TH—Electrical Throttling Energy Threshold....................... 417
4.2.14 Integrated Memory Controller DIMM Channels 
Timing Registers .................................................................................. 418
4.2.14.1 TCDBP—Timing Constraints DDR3 Bin Parameter Register............ 418