Datasheet

Datasheet, Volume 2 149
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Processor Integrated I/O (IIO) Configuration Registers
Table 3-13. IIO Control/Status and Global Error Register Map – Device 5, Function 2 –
Offset 0h–FFh
DID VID 0h
IRPPERRSV
PCISTS PCICMD 04h
CCR RID 08h
HDR CLSR 0Ch IIOERRSV
10h MIERRSV
14h PCIERRSV
18h
1Ch SYSMAP
20h VIRAL
24h ERRPINCTL
28h ERRPINST
SDID SVID 2Ch ERRPINDAT
30h
VPPCTL
CAPPTR
1
Notes:
1. CAPPTR points to the first capability block.
34h
38h VPPSTS
INTPIN INTL 3Ch BCh
PXPCAP PXPNXTPTR PXPCAPID 40h C0h
PCIe RESERVED 44h C4h
48h C8h
4Ch CCh
50h D0h
54h D4h
58h D8h
5Ch DCh
60h E0h
64h E4h
68h E8h
6Ch ECh
70h F0h
74h F4h
78h F8h
7Ch FCh