Datasheet
Datasheet, Volume 2 145
Processor Integrated I/O (IIO) Configuration Registers
3.3 Integrated I/O Core Registers
This section describes the standard PCI configuration registers and device specific
Configuration Registers related to below:
• Intel VT-d, address mapping, system management and Miscellaneous Registers –
Device 5, Function 0
• IIO control/status and Global Error Registers- Device 5, Function 2
• IOxAPIC Registers- Device 5, Function 4
3.3.1 Configuration Register Maps (Device 5, Function: 0, 2 and
4)
Table 3-9. Intel
®
VT, Address Map, System Management, Miscellaneous Registers
(Device 5, Function 0) – Offset 000h–0FFh
DID VID 00h HDRTYPECTRL 80h
PCISTS PCICMD 04h MMCFG 84h
CCR RID 08h 88h
HDR CLSR 0Ch 8Ch
10h 90h
14h 94h
18h 98h
1Ch 9Ch
20h A0h
24h A4h
28h TSEG A8h
SDID SVID 2Ch ACh
30h GENPROTRANGE1_BASE B0h
CAPPTR
1
Notes:
1. CAPPTR points to the first capability block
34h B4h
38h GENPROTRANGE1_LIMIT B8h
INTPIN INTL 3Ch BCh
PXPCAP PXPNXTPTR PXPCAPID 40h GENPROTRANGE2_BASE C0h
PCIe-Reserved 44h C4h
48h GENPROTRANGE2_LIMIT C8h
4Ch CCh
50h TOLM D0h
54h TOHM D4h
58h D8h
5Ch
DCh
60h NCMEM_BASE E0h
64h E4h
68h NCMEM_LIMIT E8h
6Ch ECh
70h MENCMEM_BASE F0h
74h F4h
78h MENCMEM_LIMIT F8h
7Ch FCh