Datasheet

Processor Integrated I/O (IIO) Configuration Registers
142 Datasheet, Volume 2
3.2.8.13 DMIRCLDECH—DMI Root Complex Link Declaration Register
This register only has meaning if placed in the configuration space.
3.2.8.14 DMIESD—DMI Element self Description Register
3.2.8.15 DMILED—DMI Link Entry Description Register
DMIRCLDECH
Bus: 0 Device: 0 Function: 0 MMIO BAR: DMIRCBAR
Offset: 40
Bit Attr
Reset
Value
Description
31:20 RO 080h Pointer to Next Capability
19:16 RO 1h
Capability Version
Indicates capability structure version
15:0 RO 0005h
Extended Capability ID
Indicates Root Complex Link Declaration capability structure.
DMIESD
Bus: 0 Device: 0 Function: 0 MMIO BAR: DMIRCBAR
Offset: 44
Bit Attr
Reset
Value
Description
31:24 RO 01h Port Number
23:16 RW-O 00h Component ID
15:8 RO 01h Number of Link Entries
7:4 RV 0h Reserved
3:0 RO 2h
Element Type
Indicates Internal Root Complex Link for DMI port
DMILED
Bus: 0 Device: 0 Function: 0 MMIO BAR: DMIRCBAR
Offset: 50
Bit Attr
Reset
Value
Description
31:24 RW-O 00h Target Port Number
23:16 RW-O 00h Target Component ID
15:2 RV 0h Reserved
1RO0b
Link Type
0 = Link Points to Memory Mapped Space
1 = Link Points to Configuration Space
0RW-O 0bLink Valid