Datasheet

Datasheet, Volume 2 141
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Processor Integrated I/O (IIO) Configuration Registers
3.2.8.11 DMIVCMRCTL—DMI VCM Resource Control Register
Controls the resources associated with PCI Express Virtual Channel 0.
3.2.8.12 DMIVCMRSTS—DMI VCM Resource Status Register
Reports the Virtual Channel specific status.
DMIVCMRCTL
Bus: 0 Device: 0 Function: 0 MMIO BAR: DMIRCBAR
Offset: 38
Bit Attr
Reset
Value
Description
31 RW-LB 0b
Virtual Channel M Enable
0 = Virtual Channel is disabled.
1 = Virtual Channel is enabled. See exceptions below.
Software must use the VC Negotiation Pending bit to check whether the VC
negotiation is complete. When VC Negotiation Pending bit is cleared, a 1 read from
this VC Enable bit indicates that the VC is enabled (Flow Control Initialization is
completed for the PCI Express port). A 0 read from this bit indicates that the
Virtual Channel is currently disabled.
BIOS Requirement:
1. To enable a Virtual Channel, the VC Enable bits for that Virtual Channel must
be set in both Components on a Link.
2. To disable a Virtual Channel, the VC Enable bits for that Virtual Channel must
be cleared in both Components on a Link.
3. Software must ensure that no traffic is using a Virtual Channel at the time it
is disabled.
4. Software must fully disable a Virtual Channel in both Components on a Link
before re-enabling the Virtual Channel.
30:27 RV 0h Reserved
26:24 RW-LB 000b VCm ID
23:8 RV 0h Reserved
7RO 1b
Traffic Class 7/ Virtual Channel 0 Map
Traffic Class 7 is always routed to VCm.
6:1 RO 0h
Traffic Class / Virtual Channel M Map
No other traffic class is mapped to VCM
0RO 0bTraffic Class 0 Virtual Channel Map
DMIVCMRSTS
Bus: N Device: 0 Function: 0 MMIO BAR: DMIRCBAR
Offset: 3E
Bit Attr
Reset
Value
Description
15:2 RV 0h Reserved
1RO-V 1b
Virtual Channel 0 Negotiation Pending
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation (initialization or
disabling).
This bit indicates the status of the process of Flow Control initialization. It is set by
default on Reset, as well as whenever the corresponding Virtual Channel is
Disabled or the Link is in the DL_Down state.
It is cleared when the link successfully exits the FC_INIT2 state.
BIOS Requirement: Before using a Virtual Channel, software must check
whether the VC Negotiation Pending fields for that Virtual Channel are cleared in
both Components on a Link.
0RV0hReserved