Datasheet
14 Datasheet, Volume 2
4.2.11.39RIRILV5OFFSET_4—RIR Range Rank Interleave 5
OFFSET Register .....................................................................378
4.2.11.40RIRILV6OFFSET_4—RIR Range Rank Interleave 6
OFFSET Register .....................................................................379
4.2.11.41RIRILV7OFFSET_4—RIR Range Rank Interleave 7
OFFSET Register .....................................................................379
4.2.12 Integrated Memory Controller Error Injection Registers..............................380
4.2.12.1 PXPENHCAP—PCI Express* Capability Register............................380
4.2.12.2 RIRWAYNESSLIMIT_[0:4]—RIR Range Wayness and
Limit Register .........................................................................380
4.2.12.3 RIRILV0OFFSET_[0:4]—RIR Range Rank Interleave 0
OFFSET Register .....................................................................381
4.2.12.4 RIRILV1OFFSET_[0:4]—RIR Range Rank Interleave 1
OFFSET Register .....................................................................381
4.2.12.5 RIRILV2OFFSET_[0:4]—RIR Range Rank Interleave 2
OFFSET Register .....................................................................382
4.2.12.6 RIRILV3OFFSET_[0:4]—RIR Range Rank Interleave 3
OFFSET Register .....................................................................382
4.2.12.7 RIRILV4OFFSET_[0:4]—RIR Range Rank Interleave 4
OFFSET Register .....................................................................383
4.2.12.8 RIRILV5OFFSET_[0:4]—RIR Range Rank Interleave 5
OFFSET Register .....................................................................383
4.2.12.9 RIRILV6OFFSET_[0:4]—RIR Range Rank Interleave 6
OFFSET Register .....................................................................384
4.2.12.10RIRILV7OFFSET_[0:4]—RIR Range Rank Interleave 7
OFFSET Register .....................................................................384
4.2.12.11RIRILV0OFFSET_1—RIR Range Rank Interleave 0
OFFSET Register .....................................................................385
4.2.12.12RIRILV1OFFSET_1—RIR Range Rank Interleave 1
OFFSET Register .....................................................................385
4.2.12.13RIRILV2OFFSET_1—RIR Range Rank Interleave 2
OFFSET Register .....................................................................386
4.2.12.14RIRILV3OFFSET_1—RIR Range Rank Interleave 3
OFFSET Register .....................................................................386
4.2.12.15RIRILV4OFFSET_1—RIR Range Rank Interleave 4
OFFSET Register .....................................................................387
4.2.12.16RIRILV5OFFSET_1—RIR Range Rank Interleave 5
OFFSET Register .....................................................................387
4.2.12.17RIRILV6OFFSET_1—RIR Range Rank Interleave 6
OFFSET Register .....................................................................388
4.2.12.18RIRILV7OFFSET_1—RIR Range Rank Interleave 7
OFFSET Register .....................................................................388
4.2.12.19RIRILV0OFFSET_2—RIR Range Rank Interleave 0
OFFSET Register .....................................................................389
4.2.12.20RIRILV1OFFSET_2—RIR Range Rank Interleave 1
OFFSET Register .....................................................................389
4.2.12.21RIRILV2OFFSET_2—RIR Range Rank Interleave 2
OFFSET Register .....................................................................390
4.2.12.22RIRILV3OFFSET_2—RIR Range Rank Interleave 3
OFFSET Register .....................................................................390
4.2.12.23RIRILV4OFFSET_2—RIR Range Rank Interleave 4
OFFSET Register .....................................................................391
4.2.12.24RIRILV5OFFSET_2—RIR Range Rank Interleave 5
OFFSET Register .....................................................................391
4.2.12.25RIRILV6OFFSET_2—RIR Range Rank Interleave 6
OFFSET Register .....................................................................392
4.2.12.26RIRILV7OFFSET_2—RIR Range Rank Interleave 7
OFFSET Register .....................................................................393
4.2.12.27RIRILV0OFFSET_3—RIR Range Rank Interleave 0
OFFSET Register .....................................................................393
4.2.12.28RIRILV1OFFSET_3—RIR Range Rank Interleave 1
OFFSET Register .....................................................................394