Datasheet

Datasheet, Volume 2 135
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Processor Integrated I/O (IIO) Configuration Registers
3.2.8.1 DMIVC0RCAP—DMI VC0 Resource Capability Register
3.2.8.2 DMIVC0RCTL—DMI VC0 Resource Control Register
Controls the resources associated with PCI Express Virtual Channel 0.
DMIVC0RCAP
Bus: 0 Device: 0 Function: 0 MMIO BAR: DMIRCBAR
Offset: 10
Bit Attr
Reset
Value
Description
31:16 RO 0000h Max Time Slots
15 RO 0h
Reject Snoop Transactions
0 = Transactions with or without the No Snoop bit set within the TLP header
are allowed on this VC.
1 = Any transaction without the No Snoop bit set within the TLP header will
be rejected as an Unsupported Request.
14:0 RV 0h Reserved
DMIVC0RCTL
Bus: 0 Device: 0 Function: 0 MMIO BAR: DMIRCBAR
Offset: 14
Bit Attr
Reset
Value
Description
31 RO 1b
Virtual Channel 0 Enable
For VC0, this is hardwired to 1 and read only as VC0 can never be disabled.
30:27 RV 0h Reserved
26:24 RO 0h
Virtual Channel 0 ID
Assigns a VC ID to the VC resource. For VC0, this is hardwired to 0 and read
only.
23:8 RV 0h Reserved
7RO 0b
Traffic Class 7/ Virtual Channel 0 Map
Traffic Class 7 is always routed to VCm.
6:1 RW-LB 3Fh
Traffic Class / Virtual Channel 0 Map
Indicates the TCs (Traffic Classes) that are mapped to the VC resource. Bit
locations within this field correspond to TC values.For example, when bit 6 is
set in this field, TC6 is mapped to this VC resource. When more than one bit
in this field is set, it indicates that multiple TCs are mapped to the VC
resource. In order to remove one or more TCs from the TC/VC Map of an
enabled VC, software must ensure that no new or outstanding transactions
with the TC labels are targeted at the given Link.
0RO 1b
Traffic Class 0 / Virtual Channel 0 Map
Traffic Class 0 is always routed to VC0.