Datasheet

Datasheet, Volume 2 129
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Processor Integrated I/O (IIO) Configuration Registers
7:6 RW 00b
Compare Mode
This field defines how the PMC (compare) register is to be used.
00 = compare mode disabled (PMC register not used)
01 = max compare only: The PMC register value is compared with the counter
value. If the counter value is greater then the Compare Status (CMPSTAT)
will be set.
10 = max compare with update of PMC at end of sample: The PMC register value
is compared with the counter value, and if the counter value is greater, the
PMC register is updated with the counter value. Note, the Compare Status
field is not affected in this mode.
11 = Reserved
5RW0b
PM Status Signal Output
0 = Level output from status/overflow signals.
1 = Pulsed output from status/overflow signals.
4:3 RW 00b
PerfMon Trigger Output
This field selects what the signal is communicated to the chip’s event logic
structure.
00 = No cluster trigger output from PerfMons or header match.
01 = PM Status.
10 = PM Event Detection.
11 = Reserved
2RW1C0b
Compare Status
This status bit captures a count compare event. The Compare Status field can be
programmed to allow this bit to be driven to Global Event (GE[3:0]) signals
which will then distribute the event to the debug logic.
0 = no event
1 = count compare – PMD counter greater than PMC register when in compare
mode.
This bit remains set once an event is reported even though the original condition
is no longer valid. Writing a logic 1 clears the bit.
1RW1C0b
Overflow Status Bit
This status bit captures the overflow event from the PMD counter. This bit
remains set once an event is reported even though the original condition is no
longer valid. Writing a logic 1 clears the bit.
0RW0b
Counter Reset
Setting this bit resets the PMD counter, the associated adder storage register and
the count mode state latch (see bits CNTMD) to the default state. It does not
change the state of this PMR register, the event selections, or the value in the
compare register.
Note: This bit must be cleared by software, otherwise the counters remain in
reset. There is also a reset bit in the PERFCON register which clears all PM
registers including the PMR.
XPPMR[0:1]
Bus: 0 Device: 0 Function: 0 Offset: 494, 498
Bus: 0 Device: 2 Function: 0 Offset: 494, 498
Bus: 0 Device: 3 Function: 0 Offset: 494, 498
Bit Attr
Reset
Value
Description