Datasheet

Processor Integrated I/O (IIO) Configuration Registers
128 Datasheet, Volume 2
15:14 RW 00b
Count Mode
This field sets how the events will be counted.
00 = Count clocks when event is logic high. Counting is level sensitive,
whenever the event is logic 1 the counter is enabled to count.
01 = Count rising edge events. Active low signals should be inverted with
EVPOLINV for correct measurements.
10 = Latch event and count clocks continuously. After the event is asserted,
latch this state and count clocks continuously. The latched state of this
condition is cleared by xxxPMRx.CNTRST bit, or PERFCON.GBRST, or
GE[3:0].
11 = Enable FIFO (push/pop) queue histogram measurement.
This mode will enable histogram measurements on PM0. This mode enable logic
to perform the function listed in the table below. The measurement cycle will not
begin until the Qempty signal is asserted. Refer to xref.
FIFO queue histogram table
FIFOn_Push FIFOn_POP PMD Adder control
00Add zero
1 0 Add queue bus value*
0 1 Sub queue bus value*
11Add zero
The latched condition of the Qempty signal cannot be cleared by PMR.CLREVLAT.
A new measurement cycle requires clearing all counters and the latched value by
asserting either PMRx.CNTRST or PERFCON.GBRST.
13:11 RW 000b
Counter enable source
These bits identify which input enables the counter. Reset Value disables
counting.
000 = Disabled
001 = Local Count Enabled (LCEN). This bit is always a logic 1.
010 = Partner counter’s event status (max compare or overflow)
011 = Reserved
100 = GE[0], from the Global Debug Event Block
101 = GE[1], from the Global Debug Event Block
110 = GE[2], from the Global Debug Event Block
111 = GE[3], from the Global Debug Event Block
Note: Address/Header MatchOut signal must align with PMEVL,H events for this
to be effective.
10:8 RW 000b
Reset Event Select
Counter and event status will reset and counting will continue.
000 = No reset condition
001 = Partner’s event status: When the partner counter causes an event status
condition to be activated, either by a counter overflow or max
comparison, then this counter will reset and continue counting.
010 = Partners PME register event: When the partner counter detects a match
condition which meets its selected PME register qualifications, then this
counter will reset and continue counting.
011 = This PM counter’s status output.
100 = GE[0], from the Global Debug Event Block.
101 = GE[1], from the Global Debug Event Block.
110 = GE[2], from the Global Debug Event Block.
111 = GE[3], from the Global Debug Event Block.
XPPMR[0:1]
Bus: 0 Device: 0 Function: 0 Offset: 494, 498
Bus: 0 Device: 2 Function: 0 Offset: 494, 498
Bus: 0 Device: 3 Function: 0 Offset: 494, 498
Bit Attr
Reset
Value
Description