Datasheet

Datasheet, Volume 2 127
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Processor Integrated I/O (IIO) Configuration Registers
3.2.7.5 XPPMR[0:1]—XP PM Response Control Register
The PMR register controls operation of its associated counter, and provides overflow or
max compare status information.
XPPMR[0:1]
Bus: 0 Device: 0 Function: 0 Offset: 494, 498
Bus: 0 Device: 2 Function: 0 Offset: 494, 498
Bus: 0 Device: 3 Function: 0 Offset: 494, 498
Bit Attr
Reset
Value
Description
31 RV 0h Reserved
30 RW 0b
Not greater than comparison
0 = PMC will compare a greater than function. When clear the perfmon status
will assert when the PMD is greater than the PMC.
1 = PMC will compare with NOT (greater than) function. When set the perfmon
status will assert when the PMD is less than or equal to the PMC.
29 RW 0b
Force PMD counter to add zero to input
This feature is used with the queue measurement bus. When this bit is set the
value on the queue measurement bus is added to zero so the result in PMD will
always reflect the value from the queue measurement bus.
0 = Do not add zero. Normal PerfMon operation.
1 = Add zero with input queue bus.
28 RW 0b
Latched Count Enable Select
0 = Normal PM operation. Use CENS as count enable.
1 = Use Latched count enable from queue empty events
27 RW 0b
Reset Pulse Enable
Setting this bit will select a pulsed version of the reset signal source in the reset
block.
0 = Normal reset signaling
1 = Select a pulsed reset from the reset signal sources.
26:24 RV 0h Reserved
20:19 RW 0h
Event Group Selection
Selects which event register to use for performance monitoring.
00 = Bus events (XPMEVL,H register) and also Resource Utilizations (XP_PMER
Registers) when all XP_PMEH and XP_PMEL Registers are set to ’0’. That is,
when monitoring PMER events, all PMEV events are to be deselected; when
monitoring PMEV events, all PMER events are to be deselected.
01 = Reserved
10 = Queue measurement (in the XPPMER register). 
Note: To enable FIFO queue histogramming write bit field CNTMD =’11’
and select queues in the XPPMER register.
11 = Reserved
18:17 RW 00b
Count Event Select
Selects the condition for incrementing the performance monitor counter.
00 = Event source selected by PMEV{L,H}
01 = Partner event status (max compare or overflow)
10 = All clocks when enabled
11 = Reserved
16 RW 0b
Event Polarity Invert
This bit inverts the polarity of the conditioned event signal.
0 = No inversion
1 = Invert the polarity of the conditioned event signal