Datasheet

Processor Integrated I/O (IIO) Configuration Registers
126 Datasheet, Volume 2
3.2.7.3 XPPMDH—XP PM Data High Bits Register
This register contains the high nibbles from each of the PMD 36-bit counter register.
3.2.7.4 XPPMCH—XP PM Compare High Bits Register
This register contains the high nibbles from each of the PMC 36-bit compare registers.
XPPMDH
Bus: 0 Device: 0 Function: 0 Offset: 490
Bus: 0 Device: 2 Function: 0 Offset: 490
Bus: 0 Device: 3 Function: 0 Offset: 490
Bit Attr
Reset
Value
Description
15:12 RV 0h Reserved
11:8 RW-V 0h
High Nibble PEX Counter1 value
High order bits [35:32] of the 36-bit PM Data1 register.
7:4 RV 0h Reserved
3:0 RW-V 0h
High Nibble PEX Counter0 value
High order bits [35:32] of the 36-bit PM Data0 register.
XPPMCH
Bus: 0 Device: 0 Function: 0 Offset: 492
Bus: 0 Device: 2 Function: 0 Offset: 492
Bus: 0 Device: 3 Function: 0 Offset: 492
Bit Attr
Reset
Value
Description
15:12 RV 0h Reserved
11:8 RW Fh
High Nibble PEX Compare1 value
High order bits [35:32] of the 36-bit PM Compare1 register.
7:4 RV 0h Reserved
3:0 RW Fh
High Nibble PEX Compare0 value
High order bits [35:32] of the 36-bit PM Compare0 register.