Datasheet

Datasheet, Volume 2 125
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Processor Integrated I/O (IIO) Configuration Registers
3.2.7 PCI Express* and DMI2 Perfmon
3.2.7.1 XPPMDL[0:1]—XP PM Data Low Bits Register
This is the performance monitor counter. This counter is reset at the beginning of a
sample period unless pre-loaded with a sample value. Therefore, the counter can cause
an early overflow condition with values loaded into the register.
3.2.7.2 XPPMCL[0:1]—XP PM Compare Low Bits Register
The value of PMD is compared to the value of PMC. If PMD is greater than PMC, this
status is reflected in the PERFCON register and/or on the GE[3:0] (TBD) as selected in
the Event Status Output field of the PMR register.
2:0 RW-O 2h
Upstream Component Transmitter Preset
Transmitter Preset for an Upstream Component. The Root Ports are upstream
components. The encodings are defined below.
000b = -6 dB for de-emphasis, 0 dB for preshoot
001b = -3.5 dB for de-emphasis, 0 dB for preshoot
010b = -6 dB for de-emphasis, -3.5 dB for preshoot
011b = -3.5 dB for de-emphasis, -3.5 dB for preshoot
100b = -0 dB for de-emphasis, 0 dB for preshoot
101b = -0 dB for de-emphasis, -3.5 dB for preshoot
others = reserved
LN[8:15]EQ
Bus: 0 Device: 2 Function: 0 Offset: 26Ch, 26Eh, 270h, 272h, 274h, 276h, 278h, 278h
Bus: 0 Device: 3 Function: 0 Offset: 26Ch, 26Eh, 270h, 272h, 274h, 276h, 278h, 278h
Bit Attr
Reset
Value
Description
XPPMDL[0:1]
Bus: 0 Device: 0 Function: 0 Offset: 480, 484
Bus: 0 Device: 2 Function: 0 Offset: 480, 484
Bus: 0 Device: 3 Function: 0 Offset: 480, 484
Bit Attr
Reset
Value
Description
31:0 RW-V 0h
PM data counter low value
Low order bits [31:0] for PM data counter[1:0].
XPPMCL[0:1]
Bus: 0 Device: 0 Function: 0 Offset: 488, 48C
Bus: 0 Device: 2 Function: 0 Offset: 488, 48C
Bus: 0 Device: 3 Function: 0 Offset: 488, 48C
Bit Attr
Reset
Value
Description
31:0 RW
FFFFFFF
Fh
PM compare low value
Low order bits [31:0] for PM compare register [1:0].