Datasheet

12 Datasheet, Volume 2
4.2.5.8 MMCFG_Target_LIST—MMCFG Target List Register ......................335
4.2.5.9 MMIO_Target_LIST—MMIO Target List Register...........................335
4.2.5.10 IOAPIC_Target_LIST—IOAPIC Target List Register.......................336
4.2.5.11 SAD_Target—SAD Target List ...................................................336
4.2.5.12 SAD_Control—SAD Control Register...........................................337
4.2.6 Integrated Memory Controller Target Address Registers.............................337
4.2.6.1 PXPCAP—PCI Express* Capability Register..................................337
4.2.6.2 MCMTR—MC Memory Technology Register ..................................338
4.2.6.3 TADWAYNESS_[0:11]—TAD Range Wayness, Limit and 
Target Register.......................................................................339
4.2.6.4 MCMTR2—MC Memory Technology Register 2..............................339
4.2.6.5 MC_INIT_STATE_G—Initialization State for Boot, Training 
and IOSAV Register.................................................................340
4.2.6.6 RCOMP_TIMER—RCOMP Wait Timer Register...............................341
4.2.7 Integrated Memory Controller MemHot Registers ......................................342
4.2.7.1 MH_MAINCNTL—MEMHOT Main Control Register..........................342
4.2.7.2 MH_SENSE_500NS_CFG—MEMHOT Sense and 500 ns 
Config Register .......................................................................343
4.2.7.3 MH_DTYCYC_MIN_ASRT_CNTR_[0:1]—MEMHOT Duty Cycle 
Period and Min Assertion Counter Register..................................343
4.2.7.4 MH_IO_500NS_CNTR—MEMHOT Input Output and 500ns 
Counter Register.....................................................................344
4.2.7.5 MH_CHN_ASTN—MEMHOT Domain Channel Association Register ...345
4.2.7.6 MH_TEMP_STAT—MEMHOT Temperature Status Register..............346
4.2.7.7 MH_EXT_STAT Register............................................................347
4.2.8 Integrated Memory Controller SMBus Registers.........................................347
4.2.8.1 SMB_STAT_[0:1]—SMBus Status Register ..................................347
4.2.8.2 SMBCMD_[0:1]—SMBus Command Register................................349
4.2.8.3 SMBCntl_[0:1]—SMBus Control Register ....................................350
4.2.8.4 SMB_TSOD_POLL_RATE_CNTR_[0:1]—SMBus Clock Period 
Counter Register.....................................................................351
4.2.8.5 SMB_STAT_1—SMBus Status Register........................................352
4.2.8.6 SMBCMD_1—SMBus Command Register.....................................353
4.2.8.7 SMBCntl_1—SMBus Control Register..........................................354
4.2.8.8 SMB_TSOD_POLL_RATE_CNTR_1—SMBus Clock Period 
Counter Register.....................................................................355
4.2.8.9 SMB_PERIOD_CFG—SMBus Clock Period Config Register ..............356
4.2.8.10 SMB_PERIOD_CNTR—SMBus Clock Period Counter Register ..........356
4.2.8.11 SMB_TSOD_POLL_RATE—SMBus TSOD POLL RATE Register..........356
4.2.9 Integrated Memory Controller DIMM Memory Technology Type Registers......357
4.2.9.1 PXPCAP—PCI Express* Capability Register..................................357
4.2.9.2 DIMMMTR_[0:2]—DIMM Memory Technology Register..................358
4.2.10 Integrated Memory Controller Memory Target Address Decoder Registers.....359
4.2.10.1 TADCHNILVOFFSET_[0:11]—TAD Range Channel Interleave i 
OFFSET Register .....................................................................359
4.2.11 Integrated Memory Controller Channel Rank Registers...............................360
4.2.11.1 RIRWAYNESSLIMIT_[0:4]—RIR Range Wayness and 
Limit Register .........................................................................360
4.2.11.2 RIRILV0OFFSET_[0:4]—RIR Range Rank Interleave 0 
OFFSET Register .....................................................................360
4.2.11.3 RIRILV1OFFSET_[0:4]—RIR Range Rank Interleave 1 
OFFSET Register .....................................................................361
4.2.11.4 RIRILV2OFFSET_[0:4]—RIR Range Rank Interleave 2 
OFFSET Register .....................................................................361
4.2.11.5 RIRILV3OFFSET_[0:4]—RIR Range Rank Interleave 3 
OFFSET Register .....................................................................362
4.2.11.6 RIRILV4OFFSET_[0:4]—RIR Range Rank Interleave 4 
OFFSET Register .....................................................................362
4.2.11.7 RIRILV5OFFSET_[0:4]—RIR Range Rank Interleave 5 
OFFSET Register .....................................................................362