Datasheet

Datasheet, Volume 2 117
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Processor Integrated I/O (IIO) Configuration Registers
3.2.5.15 XPCOREDMASK—XP Correctable Error Detect Mask Register
This register masks other correctable errors from causing the associated
XPCORERRSTS status bit to be set.
3.2.5.16 XPGLBERRSTS—XP Global Error Status Register
This register captures a concise summary of the error logging in AER registers so that
sideband system management software can view the errors independent of the main
OS that might be controlling the AER errors.
XPCOREDMASK
Bus: 0 Device: 0 Function: 0 Offset: 228h
Bus: 0 Device: 1 Function: 0 -1 Offset: 228h
Bus: 0 Device: 2 Function: 0 -3 Offset: 228h
Bus: 0 Device: 3 Function: 0–3 Offset: 228h
Bit Attr
Reset
Value
Description
31:1 RV 0h Reserved
0RWS0bPCI link bandwidth changed Detect Mask
XPGLBERRSTS
Bus: 0 Device: 0 Function: 0 Offset: 230h
Bus: 0 Device: 1 Function: 0 -1 Offset: 230h
Bus: 0 Device: 2 Function: 0 -3 Offset: 230h
Bus: 0 Device: 3 Function: 0–3 Offset: 230h
Bit Attr
Reset
Value
Description
15:3 RV 0h Reserved
2RW1CS 0b
PCIe AER Correctable Error
A PCIe correctable error (ERR_COR message received from externally or through
a virtual ERR_COR message generated internally) was detected anew. Note that if
that error was masked in the PCIe AER, it is not reported in this field. Software
clears this bit by writing a 1 and at that stage, only ‘subsequent’ PCIe unmasked
correctable errors will set this bit.Conceptually, per the flow of PCI Express Base
Specification 2.0 defined Error message control, this bit is set by the ERR_COR
message that is enabled to cause a System Error notification.
1RW1CS 0b
PCIe AER Non-fatal Error
A PCIe non-fatal error (ERR_NONFATAL message received from externally or
through a virtual ERR_NONFATAL message generated internally) was detected
anew. Note that if that error was masked in the PCIe AER, it is not reported in this
field. Software clears this bit by writing a 1 and at that stage only ‘subsequent’
PCIe unmasked non-fatal errors will set this bit again.
0RW1CS 0b
PCIe AER Fatal Error
A PCIe fatal error (ERR_FATAL message received from externally or through a
virtual ERR_FATAL message generated internally) was detected anew. Note that if
that error was masked in the PCIe AER, it is not reported in this field. Software
clears this bit by writing a 1 and at that stage, only ‘subsequent’ PCIe unmasked
fatal errors will set this bit.