Datasheet

Datasheet, Volume 2 115
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Processor Integrated I/O (IIO) Configuration Registers
3.2.5.11 UNCEDMASK—Uncorrectable Error Detect Status Mask Register
This register masks PCIe link related uncorrectable errors from causing the associated
AER status bit to be set.
3.2.5.12 COREDMASK—Correctable Error Detect Status Mask Register
This register masks PCIe link related correctable errors from causing the associated
status bit in AER status register to be set.
UNCEDMASK
Bus: 0 Device: 0 Function: 0 Offset: 218h
Bus: 0 Device: 1 Function: 0 -1 Offset: 218h
Bus: 0 Device: 2 Function: 0 -3 Offset: 218h
Bus: 0 Device: 3 Function: 0–3 Offset: 218h
Bit Attr
Reset
Value
Description
31:22 RV 0h Reserved
21 RWS 0b ACS Violation Detect Mask
20 RWS 0b Received an Unsupported Request Detect Mask
19 RV 0h Reserved
18 RWS 0b Malformed TLP Detect Mask
17 RWS 0b Receiver Buffer Overflow Detect Mask
16 RWS 0b Unexpected Completion Detect Mask
15 RWS 0b Completer Abort Detect Mask
14 RWS 0b Completion Time-out Detect Mask
13 RWS 0b Flow Control Protocol Error Detect Mask
12 RWS 0b Poisoned TLP Detect Mask
11:6 RV 0h Reserved
5RWS0bSurprise Down Error Detect Mask
4RWS0bData Link Layer Protocol Error Detect Mask
3:0 RV 0h Reserved
COREDMASK
Bus: 0 Device: 0 Function: 0 Offset: 1D0h
Bus: 0 Device: 1 Function: 0 -1 Offset: 21Ch
Bus: 0 Device: 2 Function: 0–3 Offset: 21Ch
Bus: 0 Device: 3 Function: 0–3 Offset: 21Ch
Bit Attr
Reset
Value
Description
31:14 RV 0h Reserved
13 RWS 0b Advisory Non-fatal Error Detect Mask
12 RWS 0b Replay Timer Time-out Detect Mask
11:9 RV 0h Reserved
8RWS0bReplay_Num Rollover Detect Mask
7RWS0bBad DLLP Detect Mask
6RWS0bBad TLP Detect Mask
5:1 RV 0h Reserved
0RWS0bReceiver Error Detect Mask