Datasheet

Processor Integrated I/O (IIO) Configuration Registers
112 Datasheet, Volume 2
3.2.5.5 XPCORERRSTS—XP Correctable Error Status Register
The contents of the next set of registers – XPCORERRSTS, XPCORERRMSK,
XPUNCERRSTS, XPUNCERRMSK, XPUNCERRSEV, XPUNCERRPTR – to be defined by the
design team based on microarchitecture. The architecture model for error logging and
escalation of internal errors is similar to that of PCI Express AER, except that these
internal errors never trigger an MSI and are always reported to the system software.
Mask bits mask the reporting of an error and severity bit controls escalation to either
fatal or non-fatal error to the internal core error logic. Internal errors detected in the
PCI Express cluster are not dependent on any other control bits for error escalation
other than the mask bit defined in these registers. All these registers are sticky.
3.2.5.6 XPCORERRMSK—XP Correctable Error Mask Register
XPCORERRSTS
Bus: 0 Device: 0 Function: 0 Offset: 200h
Bus: 0 Device: 1 Function: 0 -1 Offset: 200h
Bus: 0 Device: 2 Function: 0 -3 Offset: 200h
Bus: 0 Device: 3 Function: 0–3 Offset: 200h
Bit Attr
Reset
Value
Description
31:1 RV 0h Reserved
0RW1CS0b
PCI link bandwidth changed status
This bit is set when the logical OR of LNKSTS[15] and LNKSTS[14] goes from 0 to
1.
XPCORERRMSK
Bus: 0 Device: 0 Function: 0 Offset: 204h
Bus: 0 Device: 1 Function: 0 -1 Offset: 204h
Bus: 0 Device: 2 Function: 0 -3 Offset: 204h
Bus: 0 Device: 3 Function: 0–3 Offset: 204h
Bit Attr
Reset
Value
Description
31:1 RV 0h Reserved
0RWS0b
PCI link bandwidth Changed mask
Masks the BW change event from being propagated to the IIO core error logic as a
correctable error