Datasheet

Datasheet, Volume 2 111
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Processor Integrated I/O (IIO) Configuration Registers
3.2.5.3 ERRINJCON—PCI Express* Error Injection Control Register
3.2.5.4 CTOCTRL—Completion Timeout Control Register
ERRINJCON
Bus: 0 Device: 0 Function: 0 Offset: 1D8h
Bus: 0 Device: 1 Function: 0 -1 Offset: 1D8h
Bus: 0 Device: 2 Function: 0 -3 Offset: 1D8h
Bus: 0 Device: 3 Function: 0–3 Offset: 1D8h
Bit Attr
Reset
Value
Description
15:3 RV 0h Reserved
2RW0b
Cause a Completion Timeout Error
When this bit is written to transition from 0 to 1, one and only one error assertion
pulse is produced on the error source signal for the given port. This error will
appear equivalent to an actual error assertion because this event is OR’d into the
existing error reporting structure. To log another error, this bit must be cleared
first, before setting again. Leaving this bit in a 1 state does not produce a
persistent error condition.
Notes:
This bit is used for an uncorrectable error test
This bit must be cleared by software before creating another event.
This bit is disabled by bit 0 of this register
1RW0b
Cause a Receiver Error
When this bit is written to transition from 0 to 1, one and only one error assertion
pulse is produced on the error source signal for the given port. This error will
appear equivalent to an actual error assertion because this event is OR’d into the
existing error reporting structure. To log another error, this bit must be cleared
first, before setting again. Leaving this bit in a 1 state does not produce a
persistent error condition.
Notes:
This bit is used for an correctable error test
This bit must be cleared by software before creating another event.
This bit is disabled by bit 0 of this register
0RW-O 0b
Error Injection Disable
This bit disables the use of the PCIe error injection bits.
Notes:
This is a write once bit.
CTOCTRL
Bus: 0 Device: 0 Function: 0 Offset: 1E0h
Bus: 0 Device: 1 Function: 0–1 Offset: 1E0h
Bus: 0 Device: 2 Function: 0–3 Offset: 1E0h
Bus: 0 Device: 3 Function: 0–3 Offset: 1E0h
Bit Attr
Reset
Value
Description
31:10 RV 0h Reserved
9:8 RW 00b
XP-to-PCIe timeout select within 17 s to 64 s range
When OS selects a timeout range of 17s to 64s for XP (that affect NP tx issued to
the PCIe/DMI) using the root port’s DEVCTRL2 register, this field selects the sub-
range within that larger range, for additional controllability.
00 = 17s-30s
01 = 31s-45s
10 = 46s-64s
11 = Reserved
7:0 RV 0h Reserved