Datasheet

Processor Integrated I/O (IIO) Configuration Registers
110 Datasheet, Volume 2
3.2.5 PCI Express* and DMI2 Error Registers
The architecture model for error logging and escalation of internal errors is similar to
that of PCI Express AER, except that these internal errors never trigger an MSI and are
always reported to the system software. Mask bits mask the reporting of an error and
severity bit controls escalation to either fatal or non-fatal error to the internal core
error logic. Internal errors detected in the PCI Express cluster are not dependent on
any other control bits for error escalation other than the mask bit defined in these
registers. All these registers are sticky.
3.2.5.1 ERRINJCAP—PCI Express* Error Injection Capability Register
Defines a vendor specific capability for WHEA error injection.
3.2.5.2 ERRINJHDR—PCI Express* Error Injection Capability 
Header Register
ERRINJCAP
Bus: 0 Device: 0 Function: 0 Offset: 1D0h
Bus: 0 Device: 1 Function: 0 -1 Offset: 1D0h
Bus: 0 Device: 2 Function: 0 -3 Offset: 1D0h
Bus: 0 Device: 3 Function: 0-3 Offset: 1D0h
Bit Attr
Reset
Value
Description
31:20 RO 280h
Next Capability Offset
This field points to the next capability or 0 if there isn’t a next capability.
19:16 RO 1h
Capability Version
Set to 2h for this version of the PCI Express specification
15:0 RO 000Bh
PCI Express Extended Capability ID
Vendor Defined Capability
ERRINJHDR
Bus: 0 Device: 0 Function: 0 Offset: 1D4h
Bus: 0 Device: 1 Function: 0 -1 Offset: 1D4h
Bus: 0 Device: 2 Function: 0 -3 Offset: 1D4h
Bus: 0 Device: 3 Function: 0–3 Offset: 1D4h
Bit Attr
Reset
Value
Description
31:20 RO 00Ah
Vendor Specific Capability Length
Indicates the length of the capability structure, including header bytes.
19:16 RO 1h
Vendor Specific Capability Revision
Set to 1h for this version of the WHEA Error Injection logic.
15:0 RO 0003h
Vendor Specific ID
Assigned for WHEA Error Injection