Datasheet
Datasheet, Volume 2 11
4.2.2 CSR Register Maps ............................................................................... 283
4.2.3 CBO unicast CSRs ................................................................................ 301
4.2.3.1 RTID_Config_Pool01_Size—Ring Global Configuration Register...... 301
4.2.3.2 RTID_Config_Pool23_Size—Ring Global Configuration Register...... 301
4.2.3.3 RTID_Config_Pool45_Size—Ring Global Configuration Register...... 302
4.2.3.4 RTID_Config_Pool67_Size—Ring Global Configuration Register...... 302
4.2.3.5 VNA_Credit_Config—VNA Credit Configuration Register................ 303
4.2.3.6 PipeRspFunc—Pipe Response Function Register........................... 303
4.2.3.7 PipeDbgBusSel—Pipe Debug Bus Select Register......................... 304
4.2.3.8 SadDbgMm2 Register.............................................................. 304
4.2.3.9 Cbsads_Unicast_Cfg_Spare Register.......................................... 304
4.2.3.10 CBO_GDXC_PKT_CNTRL—CBO GDXC Packet Control Register ....... 305
4.2.3.11 RTID_Config_Pool01_Base—Ring Global Configuration Register..... 306
4.2.3.12 RTID_Config_Pool23_Base—Ring Global Configuration Register..... 307
4.2.3.13 RTID_Config_Pool45_Base—Ring Global Configuration Register..... 308
4.2.3.14 RTID_Config_Pool67_Base—Ring Global Configuration Register..... 309
4.2.3.15 RTID_Pool_Config—Ring Global Configuration Register................. 310
4.2.3.16 RTID_Config_Pool01_Base_Shadow—Ring Global
Configuration Shadow Register ................................................. 311
4.2.3.17 RTID_Config_Pool23_Base_Shadow—Ring Global
Configuration Shadow Register ................................................. 312
4.2.3.18 RTID_Config_Pool45_Base_Shadow—Ring Global
Configuration Shadow Register ................................................. 313
4.2.3.19 RTID_Config_Pool67_Base_Shadow—Ring Global
Configuration Shadow Register ................................................. 314
4.2.3.20 RTID_Pool_Config_Shadow— Ring Global
Configuration Shadow Register ................................................. 315
4.2.4 System Address Decoder Registers (CBO)................................................ 316
4.2.4.1 PAM0123—CBO SAD PAM Register ............................................ 316
4.2.4.2 PAM456—CBO SAD PAM Register.............................................. 317
4.2.4.3 SMRAMC—System Management RAM Control Register ................. 319
4.2.4.4 MESEG_BASE—Manageability Engine Base Address Register......... 320
4.2.4.5 MESEG_LIMIT—Manageability Engine Limit Address Register ........ 320
4.2.4.6 DRAM_RULE[0:9]—DRAM Rule 0 Register .................................. 321
4.2.4.7 INTERLEAVE_LIST[0:9]—DRAM Interleave List 0 Register ............ 321
4.2.4.8 DRAM_RULE_1—DRAM Rule 1 Register ...................................... 322
4.2.4.9 INTERLEAVE_LIST_1—DRAM Interleave List 1 Register ................ 322
4.2.4.10 DRAM_RULE_2—DRAM Rule 2 Register ...................................... 323
4.2.4.11 INTERLEAVE_LIST_2—DRAM Interleave List 2 Register ................ 323
4.2.4.12 DRAM_RULE_3—DRAM Rule 3 Register ...................................... 324
4.2.4.13 INTERLEAVE_LIST_3—DRAM Interleave List 3 Register ................ 324
4.2.4.14 DRAM_RULE_4—DRAM Rule 4 Register ...................................... 325
4.2.4.15 INTERLEAVE_LIST_4—DRAM Interleave List 4 Register ................ 325
4.2.4.16 DRAM_RULE_5—DRAM Rule 5 Register ...................................... 326
4.2.4.17 INTERLEAVE_LIST_5—DRAM Interleave List 5 Register ................ 326
4.2.4.18 DRAM_RULE_6—DRAM Rule 6 Register ...................................... 327
4.2.4.19 INTERLEAVE_LIST_6—DRAM Interleave List 6 Register ................ 327
4.2.4.20 DRAM_RULE_7—DRAM Rule 7 Register ...................................... 328
4.2.4.21 INTERLEAVE_LIST_7—DRAM Interleave List 7 Register ................ 328
4.2.4.22 DRAM_RULE_8—DRAM Rule 8 Register ...................................... 329
4.2.4.23 INTERLEAVE_LIST_8—DRAM Interleave List 8 Register ................ 329
4.2.4.24 DRAM_RULE_9—DRAM Rule 9 Register ...................................... 330
4.2.4.25 INTERLEAVE_LIST_9—DRAM Interleave List 9 Register ................ 330
4.2.5 Caching Agent Broadcast Registers (CBo)................................................ 331
4.2.5.1 Cbo_ISOC_Config—Cbo Isochrony Configuration Register............. 331
4.2.5.2 Cbo_Coh_Config—Cbo Coherency Configuration Register.............. 331
4.2.5.3 TOLM—Top of Low Memory Register.......................................... 332
4.2.5.4 TOHM—Top of High Memory Register......................................... 332
4.2.5.5 MMIO_RULE[0:7]—MMIO Rule 0 Register................................... 332
4.2.5.6 MMCFG_Rule—MMCFG Rule for Interleave Decoder Register ......... 334
4.2.5.7 IOPORT_Target_LIST—IO Target List Register ............................ 334