Datasheet

Datasheet, Volume 2 109
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Processor Integrated I/O (IIO) Configuration Registers
3.2.4.90 PXP2CAP—Secondary PCI Express* Extended Capability 
Header Register
3.2.4.91 LNKCON3—Link Control 3 Register
PXP2CAP
Bus: 0 Device: 1 Function: 0–1 Offset: 250h
Bus: 0 Device: 2 Function: 0–3 Offset: 250h
Bus: 0 Device: 3 Function: 0–3 Offset: 250h
Bit Attr
Reset
Value
Description
31:20 RO 280h
Next Capability Offset
This field contains the offset to the next PCI Express Extended Capability structure
or 000h if no other items exist in the linked list of capabilities.
19:16 RO 2h
Capability Version
This field is a PCI-SIG defined version number that indicates the version of the
Capability structure present. Must be 1h for this version of the specification.
15:0 RWO 0000h
PCI Express Extended Capability ID
This field is a PCI SIG defined ID number that indicates the nature and format of
the Extended Capability. PCI Express Extended Capability ID for the Secondary
PCI Express Extended Capability is 0019h.
Note: BIOS is required to write 0019h.
LNKCON3
Bus: 0 Device: 1 Function: 0–1 Offset: 254h
Bus: 0 Device: 2 Function: 0–3 Offset: 254h
Bus: 0 Device: 3 Function: 0–3 Offset: 254h
Bit Attr
Reset
Value
Description
31:2 RV 0h Reserved
1RW0b
Link Equalization Request Interrupt Enable
When Set, this bit enables the generation of interrupt to indicate that the Link
Equalization Request bit has been set.
0RW0b
Perform Equalization
When this register is 1b and a 1b is written to the `Link Retrain’ register with
`Target Link Speed’ set to 8 GT/s, the Upstream component must perform
Transmitter Equalization.