Datasheet

Processor Integrated I/O (IIO) Configuration Registers
108 Datasheet, Volume 2
3.2.4.89 PCIE_IOU_BIF_CTRL—PCIe* Port Bifurcation Control Register
PCIE_IOU_BIF_CTRL
Bus: 0 Device: 1 Function: 0 Offset: 190h
Bus: 0 Device: 2 Function: 0 Offset: 190h
Bus: 0 Device: 3 Function: 0 Offset: 190h
Bit Attr
Reset
Value
Description
15:4 RV 0h Reserved
3WO0b
Port Start Bifurcation
When software writes a 1 to this bit, IIO starts the port 0 bifurcation process.
After writing to this bit, software can poll the Data Link Layer link active bit in the
LNKSTS register to determine if a port is up and running. Once a port bifurcation
has been initiated by writing a 1 to this bit, software cannot initiate any more
write-1 to this bit (write of 0 is ok).
Note: That this bit can be written to a 1 in the same write that changes values for
bits 2:0 in this register and in that case, the new value from the write to bits 2:0
take effect.
This bit always reads a 0b.
2:0 RWS
Port Bifurcation Control
To select a Port bifurcation, software sets this field and then either
1. sets bit 3 in this register to initiate training OR
2. resets the entire Processor and on exit from that reset,
Processor will bifurcate the ports per the setting in this field.
For Device 1 Function 0:
000 = x4x4 (operate lanes 7:4 as x4, 3:0 as x4)
001 = x8
others = Reserved
For Device 2 Function 0:
000 = x4x4x4x4 (operate lanes 15:12 as x4, 11:8 as x4, 7:4 as x4 and 3:0 as x4)
001 = x4x4x8 (operate lanes 15:12 as x4, 11:8 as x4 and 7:0 as x8)
010 = x8x4x4 (operate lanes 15:8 as x8, 7:4 as x4 and 3:0 as x4)
011 = x8x8 (operate lanes 15:8 as x8, 7:0 as x8)
100 = x16
others: Reserved
Device :1 Function :0 CFG: Attr: RWS Reset Value: 001b
Device :2 Function :0 CFG: Attr: RWS Reset Value: 100b
Device :3 Function :0 CFG: Attr: RWS Reset Value: 100b