Datasheet

Processor Integrated I/O (IIO) Configuration Registers
106 Datasheet, Volume 2
11 RWS 1b
allow_1nonvc1_after_10vc1s
Allow a non-VC1 request from DMI to go after every ten VC1 request (to prevent
starvation of non-VC1).
Notes:
This bit has no effect if the port is in PCI Express mode.
10 RV 0h Reserved
9RWS0b
dispdspolling
Disables gen2 if timeout happens in polling.cfg.
8:7 RW 0b PME2ACKTOCTRL
6RW0b
Enable timeout for receiving PME_TO_ACK
When set, IIO enables the timeout to receiving the PME_TO_ACK
5RW-V 0b
Send PME_TURN_OFF message
When this bit is set to 1, IIO sends a PME_TURN_OFF message to the PCIe link.
Hardware clears this bit when the message has been sent on the link.
4RW0b
Enable System Error only for AER
Applies only to root ports. For Device 0 in DMI mode, this bit is to be left at default
value always. When this bit is set, the PCI Express errors do not trigger an MSI or
Intx interrupt, regardless of the whether MSI or INTx is enabled or not. Whether
or not PCI Express errors result in a system event like NMI/SMI/PMI/CPEI is
dependent on whether the appropriate system error or override system error
enable bits are set or not.
When this bit is clear, PCI Express errors are reported using MSI or INTx and/or
NMI/SMI/MCA/CPEI. .
3 RW 0b
Enable_ACPI_mode_for_Hotplug
This bit applies only to root ports. For Device 0 in DMI mode, this bit is to be left
at the Reset Value always. When this bit is set, all Hot Plug events from the PCI
Express port are handled using _HPGPE messages to the PCH and no MSI/INTx
messages are ever generated for Hot Plug events (regardless of whether MSI or
INTx is enabled at the root port or not) at the root port.
When this bit is clear, _HPGPE message generation on behalf of root port Hot Plug
events is disabled and OS can chose to generate MSI or INTx interrupt for Hot
Plug events, by setting the MSI enable bit in the Section 3.3.5.22, “MSICTRL: MSI
Control” on page 188 in root ports. This bit does not apply to the DMI ports. Refer
to PCI Express Base Specification, Revision 2.0 and Chapter 10, 'PCI Express Hot
Plug Interrupts,' for details of MSI and GPE message generation for hot plug
events. Clearing this bit (from being 1) schedules a Deassert_HPGPE event on
behalf of the root port, provided there was any previous Assert_HPGPE message
that was sent without an associated Deassert message. Note that this bit applies
to Device 3/Fn#0 in NTB mode as well and BIOS needs to set it up appropriately
in that mode.
2RW0b
Enable_ACPI_mode_for_PM
This bit applies only to root ports. For Dev#0 in DMI mode, this bit is to be left at
default value always.When this bit is set, all PM events at the PCI Express port are
handled via _PMEGPE messages to the ICH, and no MSI interrupts are ever
generated for PM events at the root port (regardless of whether MSI in the Section
3.3.5.22, “ : MSI Control” on page 188 is enabled at the root port or not). When
clear, _PMEGPE message generation for PM events is disabled and OS can chose
to generate MSI interrupts for delivering PM events by setting the MSI enable bit
in root ports. This bit does not apply to the DMI ports. Refer to PCI Express Base
Specification, Revision 2.0 and Chapter 19, 'Power Management,' for details of
MSI and GPE Clearing this bit (from being 1) schedules a Deassert_PMEGPE event
on behalf of the root port, provided there was any previous Assert_PMEGPE
message that was sent without an associated Deassert message. Note that this bit
applies to Dev#3/Fn#0 in NTB mode as well and BIOS needs to set it up
appropriately in that mode.
1RW-O obEnable Inbound Configuration Requests
MISCCTRLSTS
Bus: 0 Device: 0 Function: 0 Offset: 188h
Bus: 0 Device: 1 Function: 0–1 Offset: 188h
Bus: 0 Device: 2 Function: 0–3 Offset: 188h
Bus: 0 Device: 3 Function: 0–3 Offset: 188h
Bit Attr
Reset
Value
Description