Datasheet

Datasheet, Volume 2 105

Processor Integrated I/O (IIO) Configuration Registers
27 RWS 0b
System Interrupt Only on Link BW/Management Status
This bit, when set, will disable generating MSI and Intx interrupts on link
bandwidth (speed and/or width) and management changes, even if MSI or INTx is
enabled (that is, will disable generating MSI or INTx when LNKSTS bits 15 and 14
are set). Whether or not this condition results in a system event like SMI/PMI/
CPEI is dependent on whether this event masked or not in the XPCORERRMSK
register.
When Device 3 is operation in NTB mode, this bit still applies and BIOS needs to
do the needful if it wants to enable/disable these events from generating MSI/
INTx interrupts from the NTB device.
26 RW 0b
EOI Forwarding Disable – Disable EOI broadcast to this PCIe link
1 = EOI message will not be broadcast down this PCIe link.
0 = The port is a valid target for EOI broadcast.
BIOS must set this bit on a port if it is connected to another processor NTB or root
port on other end of the link.
25 RO 0b
Peer-to-peer Memory Write Disable
When set, peer-to-peer memory writes are master aborted; otherwise, they are
allowed to progress per the peer-to-peer decoding rules.
This has not be implemented and so is read-only.
24 RW 0b
Peer-to-peer Memory Read Disable
When set, peer-to-peer memory reads are master aborted; otherwise, they are
allowed to progress per the peer-to-peer decoding rules.
23 RW 0b
Phold Disable
Applies only to Device 0. When set, the IIO responds with Unsupported request on
receiving assert_phold message from PCH and results in generating a fatal error.
22 RWS 0b check_cpl_tc
21 RW-O 0b
Force Outbound TC to Zero
Forces the TC field to zero for outbound requests.
1 = TC is forced to zero on all outbound transactions regardless of the source TC
value
0 = TC is not altered
Note:
In DMI mode, TC is always forced to zero and this bit has no effect.
20 RW 1b
Malformed TLP 32b address in 64b header Enable
When set, this bit enables reporting a Malformed packet when the TLP is a 32 bit
address in a 4DW header. PCI Express forbids using 4DW header sizes when the
address is less than 4 GB, but some cards may use the 4DW header anyway. In
these cases, the upper 32 bits of address are all 0.
19 RV 0h Reserved
18 RWS 0b
Disable Read Completion Combining
When set, all completions are returned without combining. Completions are
naturally broken on cacheline boundaries, so all completions will be 64B or less.
17 RO 0b Force Data Parity Error
16 RO 0b Force EP Bit Error
15 RWS 0b dis_hdr_storage
14 RWS 0b allow_one_np_os
13 RWS 0b tlp_on_any_lane
12 RWS 1b disable_ob_parity_check
MISCCTRLSTS
Bus: 0 Device: 0 Function: 0 Offset: 188h
Bus: 0 Device: 1 Function: 0–1 Offset: 188h
Bus: 0 Device: 2 Function: 0–3 Offset: 188h
Bus: 0 Device: 3 Function: 0–3 Offset: 188h
Bit Attr
Reset
Value
Description