Datasheet

Processor Integrated I/O (IIO) Configuration Registers
104 Datasheet, Volume 2
37 RW 0b
Disable MCTP Broadcast to this link
When set, this bit will prevent a broadcast MCTP message (w/ Routing Type of
’Broadcast from RC’) from being sent to this link. This bit is provided as a general
chicken bit in case there are devices that barf when they receive this message or
for the case where peer-to-peer posted traffic is to be specifically prohibited to
this port to avoid deadlocks, like can happen if this port is the ’problematic’ port.
36 RWS 0b
Form-Factor
Indicates what form-factor a particular root port controls
0 = CEM
1 = Express Module
This bit is used to interpret bit 6 in the VPP serial stream for the port as either
MRL# (CEM) input or EMLSTS# (Express Module) input.
35 RW 0b
Override System Error on PCIe Fatal Error Enable
When set, fatal errors on PCI Express (that have been successfully propagated to
the primary interface of the port) are sent to the IIO core error logic (for further
escalation) regardless of the setting of the equivalent bit in the ROOTCTRL
register. When clear, the fatal errors are only propagated to the IIO core error
logic if the equivalent bit in ROOTCTRL register is set.
For Device 0 in DMI mode and Device 3/Function 0, unless this bit is set, DMI/NTB
link related fatal errors will never be notified to system software.
34 RW 0b
Override System Error on PCIe Non-fatal Error Enable
When set, non-fatal errors on PCI Express (that have been successfully
propagated to the primary interface of the port) are sent to the IIO core error
logic (for further escalation) regardless of the setting of the equivalent bit in the
ROOTCTRL register. When clear, the non-fatal errors are only propagated to the
IIO core error logic if the equivalent bit in ROOTCTRL register is set.
For Device 0 in DMI mode and Device 3/Function 0, unless this bit is set, DMI/NTB
link related non-fatal errors will never be notified to system software.
33 RW 0b
Override System Error on PCIe Correctable Error Enable
When set, correctable errors on PCI Express (that have been successfully
propagated to the primary interface of the port) are sent to the IIO core error
logic (for further escalation) regardless of the setting of the equivalent bit in the
ROOTCTRL register. When clear, the correctable errors are only propagated to the
IIO core error logic if the equivalent bit in ROOTCTRL register is set.
For Device 0 in DMI mode and Device 3/Function 0, unless this bit is set, DMI/NTB
link related correctable errors will never be notified to system software.
32 RW 0b
ACPI PME Interrupt Enable
When set, Assert/Deassert_PMEGPE messages are enabled to be generated when
ACPI mode is enabled for handling PME messages from PCI Express. See Power
Management Chapter for more details of this bit’s usage.When this bit is cleared
(from a 1), a Deassert_PMEGPE message is scheduled on behalf of the root port if
an Assert_PMEGPE message was sent last from the root port.
When NTB is enabled on Device 3/Function 0, this bit is meaningless because PME
messages are not expected to be received on the NTB link.
31 RW 0b
Disable L0s on transmitter
When set, IIO never puts its tx in L0s state, even if OS enables it using the Link
Control register.
29 RW 1b
cfg_to_en
Disables/enables config timeouts, independently of other timeouts.
28 RW 0b
to_dis
Disables timeouts completely.
MISCCTRLSTS
Bus: 0 Device: 0 Function: 0 Offset: 188h
Bus: 0 Device: 1 Function: 0–1 Offset: 188h
Bus: 0 Device: 2 Function: 0–3 Offset: 188h
Bus: 0 Device: 3 Function: 0–3 Offset: 188h
Bit Attr
Reset
Value
Description