Datasheet

Datasheet, Volume 2 103
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Processor Integrated I/O (IIO) Configuration Registers
3.2.4.86 MISCCTRLSTS—Miscellaneous Control and Status Register
2RW0b
Enable No-Snoop Optimization on VC0 reads and VCp reads
This applies to reads with the following conditions:
NS=1 AND (TPH=0 OR TPHDIS=1)
1 = When the condition is true for a given inbound read request to memory, it will
be treated as non-coherent (no snoops) reads on Intel QPI.
0 = When the condition is true for a given inbound read request to memory, it will
be treated as normal snooped reads from PCIe (which trigger a PCIRdCurrent
or DRd.UC on IDI).
Notes:
1. If TPH=1 and TPHDIS=0 then NS is ignored and this bit is ignored
2. VC1 and VCm reads are not controlled by this bit and those reads are always
non-snoop.
3. Current recommendation for BIOS is to just leave this bit at default of 0b.
1RW0bDisable reads bypassing other reads
0RW1bRead Stream Policy
MISCCTRLSTS
Bus: 0 Device: 0 Function: 0 Offset: 188h
Bus: 0 Device: 1 Function: 0–1 Offset: 188h
Bus: 0 Device: 2 Function: 0–3 Offset: 188h
Bus: 0 Device: 3 Function: 0–3 Offset: 188h
Bit Attr
Reset
Value
Description
63:52 RV 0h Reserved
51 RW 1b VCM Arbitrated in VC1
50 RW 0b No VCM Throttle in Quiesce
49 RW1CS 0b
Locked read timed out
Indicates that a locked read request incurred a completion time-out on PCI
Express/DMI
48 RW1C 0b
Received PME_TO_ACK
Indicates that IIO received a PME turn off ack packet or it timed out waiting for
the packet
47:42 RV 0h Reserved
41 RW 0b
Override SocketID in Completion ID
For TPH/DCA requests, the Completer ID can be returned with SocketID when this
bit is set.
40:39 RV 0h Reserved
38 RW 0b
’Problematic Port’ for Lock Flows
This bit is set by BIOS when it knows that this port is connected to a device that
creates Posted-Posted dependency on its In-Out queues.
Briefly, this bit is set on a link if:
• This link is connected to a processor RP or processor NTB port on the other
side of the link
IIO lock flows depend on the setting of this bit to treat this port in a special way
during the flows. If BIOS is setting up the lock flow to be in the ’ Intel QPI
compatible’ mode, then this bit must be set to 0.
Note: An inbound MSI request can block the posted channel until EOI’s are posted
to all outbound queues enabled to receive EOI. Because of this, this bit cannot be
set unless EOIFD is also set.
PERFCTRLSTS
Bus: 0 Device: 0 Function: 0 Offset: 180h
Bus: 0 Device: 1 Function: 0–1 Offset: 180h
Bus: 0 Device: 2 Function: 0–3 Offset: 180h
Bus: 0 Device: 3 Function: 0–3 Offset: 180h
Bit Attr
Reset
Value
Description