Datasheet
Processor Integrated I/O (IIO) Configuration Registers
102 Datasheet, Volume 2
3.2.4.85 PERFCTRLSTS—Performance Control and Status Register
PERFCTRLSTS
Bus: 0 Device: 0 Function: 0 Offset: 180h
Bus: 0 Device: 1 Function: 0–1 Offset: 180h
Bus: 0 Device: 2 Function: 0–3 Offset: 180h
Bus: 0 Device: 3 Function: 0–3 Offset: 180h
Bit Attr
Reset
Value
Description
63:42 RV 0h Reserved
41 RW 0b
TLP Processing Hint Disable
When set, writes or reads with TPH=1, will be treated as if TPH=0.
40 RW 0b
DCA Requester ID Override
When this bit is set, Requester ID match for DCA writes is bypassed. All writes
from the port are treated as DCA writes and the tag field will convey if DCA is
enabled or not and the target information.
39:36 RV 0h Reserved
35 RW 0b Max read request completion combining size
34:21 RV 0h Reserved
20:16 RW 18h Outstanding Requests for Gen1
15:14 RV 0h Reserved
13:8 RW 30h Outstanding Requests for Gen2
7RW0b
Use Allocating Flows for ‘Normal Writes’ on VC0 and VCp
1 = Use allocating flows for the writes that meet the following criteria.
0 = Use non-allocating flows for writes that meet the following criteria.
(TPH=0 OR TPHDIS=1 OR (TPH=1 AND Tag=0 AND CIPCTRL[28]=1)) AND
(NS=0 OR NoSnoopOpWrEn=0) AND
Non-DCA Write
Notes:
1. VC1/VCm traffic is not impacted by this bit in Device 0
2. When allocating flows are used for the above write types, IIO does not send
a Prefetch Hint message.
3. Current recommendation for BIOS is to just leave this bit at default of 1b for
all but DMI port. For DMI port when operating in DMI mode, this bit must be
left at default value and when operating in PCIe mode, this bit should be set
by BIOS.
4. There is a coupling between the usage of this bit and bits 2 and 3.
5. TPHDIS is bit 0 of this register
6. NoSnoopOpWrEn is bit 3 of this register
4RW1bRead Stream Interleave Size
3RW0b
Enable No-Snoop Optimization on VC0 writes and VCp writes
This applies to writes with the following conditions:
NS=1 AND (TPH=0 OR TPHDIS=1)
1 = Inbound writes to memory with above conditions will be treated as non-
coherent (no snoops) writes on Intel QPI
0 = Inbound writes to memory with above conditions will be treated as allocating
or non-allocating writes, depending on bit 4 in this register.
Notes:
1. If TPH=1 and TPHDIS=0, then NS is ignored and this bit is ignored
2. VC1/VCm writes are not controlled by this bit since they are always non-
snoop and can be no other way.
3. Current recommendation for BIOS is to just leave this bit at default of 0b.