Datasheet

Processor Integrated I/O (IIO) Configuration Registers
100 Datasheet, Volume 2
3.2.4.82 RPERRCMD—Root Port Error Command Register
This register controls behavior upon detection of errors.
3.2.4.83 RPERRSTS—Root Port Error Status Register
The Root Error Status register reports status of error Messages (ERR_COR),
ERR_NONFATAL, and ERR_FATAL) received by the Root Complex in IIO, and
errors detected by the Root Port itself (which are treated conceptually as if the
Root Port had sent an error Message to itself). The ERR_NONFATAL and
ERR_FATAL Messages are grouped together as uncorrectable. Each correctable
and uncorrectable (Non-fatal and Fatal) error source has a first error bit and a
next error bit associated with it respectively. When an error is received by a
Root Complex, the respective first error bit is set and the Requestor ID is
logged in the Error Source Identification register. A set individual error status
bit indicates that a particular error category occurred; software may clear an
error status by writing a 1 to the respective bit. If software does not clear the
first reported error before another error Message is received of the same
category (correctable or uncorrectable), the corresponding next error status
bit will be set but the Requestor ID of the subsequent error Message is
discarded. The next error status bits may be cleared by software by writing a 1
to the respective bit as well
.
RPERRCMD
Bus: 0 Device: 0 Function: 0 Offset: 174h
Bus: 0 Device: 1 Function: 0–1 Offset: 174h
Bus: 0 Device: 2 Function: 0–3 Offset: 174h
Bus: 0 Device: 3 Function: 0–3 Offset: 174h
Bit Attr
Reset
Value
Description
31:3 RV 0h Reserved
2RW0b
FATAL Error Reporting Enable
Applies to root ports only Enable MSI/INTx interrupt on fatal errors when set.
1RW0b
Non-FATAL Error Reporting Enable
Applies to root ports only Enable interrupt on a non-fatal error when set.
0RW0b
Correctable Error Reporting Enable
Applies to root ports only Enable interrupt on correctable errors when set.
RPERRSTS
Bus: 0 Device: 0 Function: 0 Offset: 178h
Bus: 0 Device: 1 Function: 0–1 Offset: 178h
Bus: 0 Device: 2 Function: 0–3 Offset: 178h
Bus: 0 Device: 3 Function: 0–3 Offset: 178h
Bit Attr
Reset
Value
Description
31:27 RO 0h
Advanced Error Interrupt Message Number
Advanced Error Interrupt Message Number offset between base message data an
the MSI message if assigned more than one message number. IIO hardware
automatically updates this register to 1h if the number of messages allocated to
the root port is 2.
26:7 RO 0h Reserved
6RW1CS0b
Fatal Error Messages Received
Set when one or more Fatal Uncorrectable error Messages have been received.
5RW1CS0b
Non-Fatal Error Messages Received
Set when one or more Non-Fatal Uncorrectable error Messages have been
received.