Datasheet
10 Datasheet, Volume 2
3.3.8.45 VTD1_EXT_CAP—Extended Intel
®
VT-d Capability Register ...........263
3.3.8.46 VTD1_GLBCMD—Global Command Register.................................264
3.3.8.47 VTD1_GLBSTS—Global Status Register.......................................266
3.3.8.48 VTD1_ROOTENTRYADD—Root Entry Table Address Register..........266
3.3.8.49 VTD1_CTXCMD—Context Command Register ..............................267
3.3.8.50 VTD1_FLTSTS—Fault Status Register .........................................268
3.3.8.51 VTD1_FLTEVTCTRL—Fault Event Control Register ........................269
3.3.8.52 VTD1_FLTEVTDATA—Fault Event Data Register ...........................269
3.3.8.53 VTD1_FLTEVTADDR—Fault Event Address Register ......................270
3.3.8.54 VTD1_PMEN—Protected Memory Enable Register.........................270
3.3.8.55 VTD1_PROT_LOW_MEM_BASE—Protected Memory Low
Base Register .........................................................................270
3.3.8.56 VTD1_PROT_LOW_MEM_LIMIT—Protected Memory Low
Limit Register .........................................................................271
3.3.8.57 VTD1_PROT_HIGH_MEM_BASE—Protected Memory High
Base Register .........................................................................271
3.3.8.58 VTD1_PROT_HIGH_MEM_LIMIT—Protected Memory High
Limit Register .........................................................................271
3.3.8.59 VTD1_INV_QUEUE_HEAD—Invalidation Queue Header
Pointer Register ......................................................................272
3.3.8.60 VTD1_INV_QUEUE_TAIL—Invalidation Queue Tail
Pointer Register ......................................................................272
3.3.8.61 VTD1_INV_QUEUE_ADD—Invalidation Queue
Address Register.....................................................................272
3.3.8.62 VTD1_INV_COMP_STATUS—Invalidation Completion
Status Register.......................................................................273
3.3.8.63 VTD1_INV_COMP_EVT_CTL—Invalidation Completion Event
Control Register......................................................................273
3.3.8.64 VTD1_INV_COMP_EVT_DATA—Invalidation Completion Event
Data Register..........................................................................273
3.3.8.65 VTD1_INV_COMP_EVT_ADDR—Invalidation Completion
Event Address Register ............................................................274
3.3.8.66 VTD1_INTR_REMAP_TABLE_BASE—Interrupt Remapping Table
Base Address Register .............................................................274
3.3.8.67 VTD1_FLTREC0_GPA—Fault Record Register ...............................274
3.3.8.68 VTD1_FLTREC0_SRC—Fault Record Register ...............................275
3.3.8.69 VTD1_INVADDRREG—Invalidate Address Register .......................275
3.3.8.70 VTD1_IOTLBINV—IOTLB Invalidate Register ...............................276
4 Processor Uncore Configuration Registers .............................................................277
4.1 PCI Standard Registers.....................................................................................277
4.1.1 VID—Vendor Identification Register.........................................................277
4.1.2 DID—Device Identification Register.........................................................277
4.1.3 PCICMD—PCI Command Register............................................................278
4.1.4 PCISTS—PCI Status Register..................................................................279
4.1.5 RID—Revision Identification Register.......................................................280
4.1.6 CCR—Class Code Register......................................................................280
4.1.7 CLSR—Cacheline Size Register................................................................280
4.1.8 PLAT—Primary Latency Timer Register.....................................................280
4.1.9 HDR—Header Type Register ...................................................................281
4.1.10 BIST—Built-In Self Test Register.............................................................281
4.1.11 SVID—Subsystem Vendor ID Register .....................................................281
4.1.12 SDID—Subsystem Device ID Register......................................................281
4.1.13 CAPPTR—Capability Pointer Register........................................................282
4.1.14 INTL—Interrupt Line Register.................................................................282
4.1.15 INTPIN—Interrupt Pin Register ...............................................................282
4.1.16 MINGNT—Minimum Grant Register..........................................................282
4.1.17 MAXLAT—Maximum Latency Register ......................................................282
4.2 Integrated Memory Controller Configuration Registers ..........................................283
4.2.1 Processor Registers...............................................................................283