Intel® Core™ i7 Processor Family for the LGA-2011 Socket Datasheet, Volume 2 Supporting Desktop Intel® Core™ i7-3960X Extreme Edition Processor for the LGA-2011 Socket Supporting Desktop Intel® Core™ i7-3000K and i7-3000 Processor Series for the LGA-2011 Socket This is volume 2 of 2.
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Contents 1 Introduction ............................................................................................................ 25 1.1 Document Terminology ...................................................................................... 25 1.2 Related Documents ........................................................................................... 27 1.3 Register Terminology .........................................................................................
3.2.4.32 SNXTPTR—Subsystem ID Next Pointer Register .............................62 3.2.4.33 DMIRCBAR—DMI Root Complex Register Block Base Address Register .......................................................................62 3.2.4.34 MSICAPID—MSI Capability ID Register .........................................62 3.2.4.35 MSINXTPTR—MSI Next Pointer Register........................................63 3.2.4.36 MSIMSGCTL—MSI Control Register ..............................................63 3.2.4.
3.2.5 3.2.6 3.2.7 3.2.8 Datasheet, Volume 2 3.2.4.89 PCIE_IOU_BIF_CTRL—PCIe* Port Bifurcation Control Register....... 108 3.2.4.90 PXP2CAP—Secondary PCI Express* Extended Capability Header Register...................................................................... 109 3.2.4.91 LNKCON3—Link Control 3 Register ............................................ 109 PCI Express* and DMI2 Error Registers ................................................... 110 3.2.5.
3.3 6 3.2.8.14 DMIESD—DMI Element self Description Register .......................... 142 3.2.8.15 DMILED—DMI Link Entry Description Register ............................. 142 3.2.8.16 DMILBA0—DMI Link Address Register ........................................ 143 3.2.8.17 DMIVC1CdtThrottle—DMI VC1 Credit Throttle Register ................. 143 3.2.8.18 DMIVCpCdtThrottle—DMI VCp Credit Throttle Register.................. 143 3.2.8.19 DMIVCmCdtThrottle—DMI VCm Credit Throttle Register................
VTGENCTRL—Intel® VT-d General Control Register...................... 173 VTISOCHCTRL—Intel® VT-d Isoch Related Control Register .......... 174 VTGENCTRL2—Intel® VT-d General Control 2 Register ................. 175 IOTLBPARTITION—IOTLB Partitioning Control Register ................. 176 VTUNCERRSTS—Uncorrectable Error Status Register ................... 176 VTUNCERRMSK—Intel® VT Uncorrectable Error Mask Register....... 177 VTUNCERRSEV—Intel® VT Uncorrectable Error Severity Register...
3.3.5.12 3.3.5.13 3.3.5.14 3.3.5.15 3.3.6 3.3.7 8 IRPP1ERRCTL—IRP Protocol Error Control Register ....................... 208 IRPP1FFERRST—IRP Protocol Fatal FERR Status Register .............. 209 IRPP1FNERRST—IRP Protocol Fatal NERR Status Register ............. 209 IRPP1FFERRHD[0:3]—IRP Protocol Fatal FERR Header Log 0 Register ........................................................................ 210 3.3.5.16 IRPP1NFERRST—IRP Protocol Non-Fatal FERR Status Register ....... 210 3.3.5.
3.3.8 Datasheet, Volume 2 3.3.7.5 APICID Register...................................................................... 229 3.3.7.6 VER—Version Register ............................................................. 229 3.3.7.7 ARBID—Arbitration ID Register ................................................. 230 3.3.7.8 BCFG—Boot Configuration Register ........................................... 230 3.3.7.9 RTL[0:23]—Redirection Table Low DWord Register ...................... 231 3.3.7.
3.3.8.45 3.3.8.46 3.3.8.47 3.3.8.48 3.3.8.49 3.3.8.50 3.3.8.51 3.3.8.52 3.3.8.53 3.3.8.54 3.3.8.55 3.3.8.56 3.3.8.57 3.3.8.58 3.3.8.59 3.3.8.60 3.3.8.61 3.3.8.62 3.3.8.63 3.3.8.64 3.3.8.65 3.3.8.66 3.3.8.67 3.3.8.68 3.3.8.69 3.3.8.70 4 10 VTD1_EXT_CAP—Extended Intel® VT-d Capability Register ........... 263 VTD1_GLBCMD—Global Command Register................................. 264 VTD1_GLBSTS—Global Status Register.......................................
4.2.2 4.2.3 4.2.4 4.2.5 Datasheet, Volume 2 CSR Register Maps ............................................................................... 283 CBO unicast CSRs ................................................................................ 301 4.2.3.1 RTID_Config_Pool01_Size—Ring Global Configuration Register...... 301 4.2.3.2 RTID_Config_Pool23_Size—Ring Global Configuration Register...... 301 4.2.3.3 RTID_Config_Pool45_Size—Ring Global Configuration Register...... 302 4.2.3.
4.2.5.8 MMCFG_Target_LIST—MMCFG Target List Register ...................... 335 4.2.5.9 MMIO_Target_LIST—MMIO Target List Register ........................... 335 4.2.5.10 IOAPIC_Target_LIST—IOAPIC Target List Register ....................... 336 4.2.5.11 SAD_Target—SAD Target List ................................................... 336 4.2.5.12 SAD_Control—SAD Control Register ........................................... 337 4.2.6 Integrated Memory Controller Target Address Registers .......................
4.2.11.8 RIRILV6OFFSET_[0:4]—RIR Range Rank Interleave 6 OFFSET Register ..................................................................... 363 4.2.11.9 RIRILV7OFFSET_[0:4]—RIR Range Rank Interleave 7 OFFSET Register ..................................................................... 363 4.2.11.10RIRILV0OFFSET_1—RIR Range Rank Interleave 0 OFFSET Register ..................................................................... 364 4.2.11.
4.2.11.39RIRILV5OFFSET_4—RIR Range Rank Interleave 5 OFFSET Register ..................................................................... 378 4.2.11.40RIRILV6OFFSET_4—RIR Range Rank Interleave 6 OFFSET Register ..................................................................... 379 4.2.11.41RIRILV7OFFSET_4—RIR Range Rank Interleave 7 OFFSET Register ..................................................................... 379 4.2.12 Integrated Memory Controller Error Injection Registers ...............
4.2.12.29RIRILV2OFFSET_3—RIR Range Rank Interleave 2 OFFSET Register ..................................................................... 394 4.2.12.30RIRILV3OFFSET_3—RIR Range Rank Interleave 3 OFFSET Register ..................................................................... 395 4.2.12.31RIRILV4OFFSET_3—RIR Range Rank Interleave 4 OFFSET Register ..................................................................... 395 4.2.12.32RIRILV5OFFSET_3—RIR Range Rank Interleave 5 OFFSET Register ......
4.2.14.2 TCRAP—Timing Constraints DDR3 Regular Access Parameter Register.................................................................. 419 4.2.14.3 TCRWP—Timing Constraints DDR3 Read Write Parameter Register ................................................................................. 420 4.2.14.4 TCOTHP—Timing Constraints DDR3 Other Timing Parameter Register.................................................................. 422 4.2.14.
4.3 4.4 4.2.16.10CORRERRCNT_2—Corrected Error Count Register........................ 449 4.2.16.11CORRERRCNT_3—Corrected Error Count Register........................ 450 4.2.16.12CORRERRTHRSHLD_0—Corrected Error Threshold Register........... 450 4.2.16.13CORRERRTHRSHLD_1—Corrected Error Threshold Register........... 451 4.2.16.14CORRERRTHRSHLD_2—Corrected Error Threshold Register........... 451 4.2.16.15CORRERRTHRSHLD_3—Corrected Error Threshold Register........... 451 4.2.16.
4.5 18 4.4.2.20 PRIP_TURBO_PWR_LIM—Primary Plane Turbo Power Limitation Register .................................................................. 486 4.4.2.21 PRIMARY_PLANE_CURRENT_CONFIG_CONTROL—Primary Plane Current Configuration Control Register............................... 487 4.4.3 PCU1 Registers..................................................................................... 488 4.4.3.1 SSKPD—Sticky Scratchpad Data Register.................................... 488 4.4.3.
4.6 4.7 4.8 4.5.2.7 UBOXErrSts—Error Status Register............................................ 522 4.5.2.8 EVENTS_DEBUG Register ......................................................... 523 4.5.3 ScratchPad and Semaphore Registers ..................................................... 523 4.5.3.1 BIOSScratchpad[0:7]—BIOS Scratchpad 0 Register ..................... 523 4.5.3.2 BIOSNonStickyScratchpad[0:15]—BIOS NonSticky Scratchpad 0 Register ...........................................................
4.8.7 4.8.8 4.8.9 4.8.10 4.8.11 4.8.12 4.8.13 4.8.14 4.8.15 4.8.16 4.8.17 4.8.18 4.8.19 4.8.20 4.8.21 4.8.22 4.8.23 4.8.24 4.8.25 4.8.26 4.8.27 4.8.28 4.8.29 DDRIOTXTopRank0A[0:1]—DDRIOTXTopRank0 Register ............................ 547 DDRIOCtlPICode0A[0:1]—DDRIOCtlPICode0 Register ................................ 548 DDRIOCtlPICode1A[0:1]—DDRIOCtlPICode1 Register ................................ 549 DDRIOLogicDelayA[0:1]—DDRIOLogicDelay Register .................................
3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 Device 0/Function 0 DMI2 mode), Devices 2/Functions 0 (PCIe* Root Port), and Device 3/Function 0 (PCIe* Root Port) Extended Configuration Map – Offset 400h–4FCh ............................................................................................. 46 DMI2 RCRB Registers.......................................................................................
4-12 4-13 4-14 4-15 4-16 4-17 4-18 22 Function 4, Offset 00h–FCh Memory Controller Channel 1 Thermal Control Registers: Bus N, Device 16, Function 5, Offset 00h–FCh ...............................................................................
4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 Offset 200h–2FCh Memory Controller Channel 1 Error Registers: Bus N, Device 16, Function 7, Offset 200h–2FCh ........................................................................................... 300 Processor Home Agent Registers Device: 14, Function: 0)..................................... 465 PCU0 Register Map: Device: 10 Function: 000h–104h .......................................... 472 PCU1 Register Map: Device: 10 Function: 1 ......................
Revision History Revision Number Description Date 001 • Initial release November 2011 002 • Updated to clarify references to PCI Express* November 2011 § 24 Datasheet, Volume 2
Introduction 1 Introduction This document is Volume 2 of the datasheet for the Intel® Core™ i7 processor family for the LGA-2011 socket. The complete datasheet consists of two volumes. This document provides register information. Volume 1 provides DC electrical specifications, land and signal definitions, interface functional descriptions, power management descriptions, and additional feature information pertinent to the implemtation and operation of the processor on its platform.
Introduction Table 1-1. Processor Terminology (Sheet 2 of 3) Term 26 Description Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system.
Introduction Table 1-1. Processor Terminology (Sheet 3 of 3) Term Description SMBus System Management Bus. A two-wire interface through which simple system and power management related devices can communicate with the rest of the system. It is based on the principals of the operation of the I2C* two-wire serial bus from Philips Semiconductor. SSE Intel® Streaming SIMD Extensions (Intel® SSE) Storage Conditions A non-operational state.
Introduction Table 1-2. Processor Documents (Sheet 2 of 2) Document Number/ Location Document Intel® 64 and IA-32 Architectures Software Developer's Manuals • Volume 1: Basic Architecture • Volume 2A: Instruction Set Reference, A-M • Volume 2B: Instruction Set Reference, N-Z • Volume 3A: System Programming Guide • Volume 3B: System Programming Guide http://www.intel.com/ products/processor/ manuals/index.
Introduction Table 1-3. Register Attributes Definitions (Sheet 2 of 2) Attr Description RW-LB Read/Write Lock Bypass : Similar to RWL, these bits can be read and written by software. HW can make these bits "Read Only" using a separate configuration bit or other logic. However, RWLB is a special case where the locking is controlled by the lock-bypass capability that is controlled by the lock-bypass enable bits.
Introduction 30 Datasheet, Volume 2
Configuration Process and Registers 2 Configuration Process and Registers 2.1 Platform Configuration Structure The DMI2 physically connects the processor and the PCH. From a configuration standpoint, the DMI2 is a logical extension of PCI Bus 0. DMI2 and the internal devices in the processor IIO and PCH logically constitute PCI Bus 0 to configuration software. As a result, all devices internal to the processor and the PCH appear to be on PCI Bus 0. 2.1.
Configuration Process and Registers also contains the extended PCI Express configuration space that include PCI Express error status/control registers and Isochronous and Virtual Channel controls. • Device 2: PCI Express Root Port 2a, 2b, 2c and 2d. Logically this appears as a “virtual” PCI-to-PCI bridge residing on PCI bus 0 and is compliant with PCI Express Specification Revision 3.0.
Configuration Process and Registers 2.1.2 Processor Uncore Devices (CPUBUSN0 (1)) The configuration registers for these devices are mapped as devices residing on the PCI bus assigned for the processor socket. Figure 2-2.
Configuration Process and Registers • Device 16: Integrated Memory Controller Channel 0, 1, 2 and 3. Device 16, Function 0, 1, 4 and 5 contains the Thermal control registers for Integrated Memory Controller. Channel 0 resides at DID of 3CB4h. Channel 1 resides at DID of 3CB5h. Channel 2 resides at DID of 3CB0h. Channel 3 resides at DID of 3CB1h. Device 16, Function 2, 3, 6 and 7 contains the test registers for the Integrated Memory Controller. • Device 19: Processor performance monitoring and Ring.
Configuration Process and Registers 2.3 Configuration Mechanisms The processor is the originator of configuration cycles. Internal to the processor, transactions received through both of the below configuration mechanisms are translated to the same format. 2.3.1 Standard PCI Express* Configuration Mechanism The following is the mechanism for translating processor I/O bus cycles to configuration cycles.
Configuration Process and Registers Table 2-1.
Processor Integrated I/O (IIO) Configuration Registers 3 Processor Integrated I/O (IIO) Configuration Registers 3.1 Processor IIO Devices (PCI Bus CPUBUSNO (0)) The processor IIO contains 10 PCI devices within a single, physical component. The configuration registers for the devices are mapped as devices residing on PCI Bus “CPUBUSNO(0)” where CPUBUSNO(0) is programmable by BIOS. 3.
Processor Integrated I/O (IIO) Configuration Registers Figure 3-1. DMI2 Port (Device 0) and PCI Express* Root Ports Type 1 Configuration Space Extended Configuration Space 0 xFFF VSEC- AER Capability VSEC- REUT Capability 0x 100 PCI Device Dependent PCIe Capability 0x40 CAP_ PTR Type0 Header 0x00 Note: 38 PCI Header Legacy Configuration Space PM Capability VSEC stands for Vendor Specific Extended Capability. In DMI2 mode, AER appears as a vendor specific extended capability.
Processor Integrated I/O (IIO) Configuration Registers Figure 3-2.
Processor Integrated I/O (IIO) Configuration Registers 3.2.3 IIO PCI Express* Configuration Space Registers Table 3-1.
Processor Integrated I/O (IIO) Configuration Registers Table 3-2.
Processor Integrated I/O (IIO) Configuration Registers Table 3-3.
Processor Integrated I/O (IIO) Configuration Registers Table 3-4.
Processor Integrated I/O (IIO) Configuration Registers Table 3-5.
Processor Integrated I/O (IIO) Configuration Registers Table 3-6.
Processor Integrated I/O (IIO) Configuration Registers Table 3-7.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4 Standard PCI Configuration Space (Type 0/1 Common Configuration Space) This section covers registers in the 0h to 3Fh region that are common to all the devices 0–3. Comments at the top of the table indicate what devices/functions the description applies to. Exceptions that apply to specific functions are noted in the individual bit descriptions. 3.2.4.1 VID—Vendor Identification Register Register: VID Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.2.4.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.3 PCICMD—PCI Command Register PCICMD Bus: 0 Bus: 0 Bus: 0 Bus: 0 0 1 2 3 Bit Attr Reset Value 15:11 RV 0h Reserved Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 04h 04h 04h 04h Description 10 RW 0b INTxDisable: Interrupt Disable This bit controls the ability of the PCI Express port to generate INTx messages.
Processor Integrated I/O (IIO) Configuration Registers PCICMD Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 1 0 3.2.4.4 Device: Device: Device: Device: Attr RW RO 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 04h 04h 04h 04h Reset Value Description 0b Memory Space Enable 1 = Enables a PCI Express port’s memory range registers to be decoded as valid target addresses for transactions from secondary side.
Processor Integrated I/O (IIO) Configuration Registers PCISTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 50 Device: Device: Device: Device: Attr 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 06h 06h 06h 06h Reset Value Description 12 RW1C 0b Received Target Abort This bit is set when a device experiences a completer abort condition on a transaction it mastered on the primary interface (uncore internal bus).
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.5 RID—Revision Identification Register RID Bus: Bus: Bus: Bus: 0 0 0 0 Bit Attr 7:0 3.2.4.6 RO 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 08h 08h 08h 08h Reset Value Description 00h Revision Identification Reflects the Uncore Revision ID after reset. Reflects the Compatibility Revision ID after BIOS writes 69h to any RID register in any processor function.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.8 PLAT—Primary Latency Timer Register PLAT Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.2.4.9 Device: Device: Device: Device: Bit Attr Reset Value 7:0 RO 0h 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 0Dh 0Dh 0Dh 0Dh Description Primary Latency Timer Not applicable to PCI Express. Hardwired to 00h.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.11 BIST—Built-In Self Test Register BIST Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.2.4.12 Device: Device: Device: Device: Bit Attr Reset Value 7:0 RO 0h Bit 7:0 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 0Fh 0Fh 0Fh 0Fh Description BIST Tests Not supported. Hardwired to 00h.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.15 IOBAS—I/O Base Register IOBAS Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.2.4.16 Device: Device: Device: Device: Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 1Ch (PCIe MODE) 1Ch 1Ch 1Ch Bit Attr Reset Value 7:4 RW Fh I/O Base Address This field corresponds to A[15:12] of the I/O base address of the PCI Express port. See also the IOLIM register description.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.17 SECSTS—Secondary Status Register SECSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 1Eh (PCIe MODE) 1Eh 1Eh 1Eh Bit Attr Reset Value Description 15 RW1C 0b Detected Parity Error This bit is set by the root port when it receives a poisoned TLP in the PCI Express port.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.18 MBAS—Memory Base Register MBAS Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.2.4.19 Device: Device: Device: Device: Bit Attr Reset Value 15:4 RW FFFh 3:0 RV 0h Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 20h (PCIe* MODE) 20h 20h 20h Description Memory Base Address This bit corresponds to A[31:20] of the 32-bit memory window’s base address of the PCI Express port.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.20 PBAS—Prefetchable Memory Base Register PBAS Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.2.4.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.23 PLIMU—Prefetchable Memory Limit (Upper 32 bits) Register PLIMU Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 31:0 3.2.4.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.25 SDID—Subsystem Identity SDID Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.2.4.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.29 INTPIN—Interrupt Pin Register INTPIN Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 7:0 3.2.4.30 Device: Device: Device: Device: Attr RW-O Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 3Dh 3Dh 3Dh 3Dh Reset Value Description 01h Interrupt Pin The only allowed values in this register are 00h and 01h.
Processor Integrated I/O (IIO) Configuration Registers BCTRL Bus: 0 Bus: 0 Bus: 0 Bus: 0 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 3Eh(PCIe* MODE) 3Eh 3Eh 3Eh Bit Attr Reset Value 5 RO 0b Master Abort Mode Not applicable to PCI Express. This bit is hardwired to 0. 0b VGA 16-bit Decode This bit enables the virtual PCI-to-PCI bridge to provide 16-bit decoding of VGA I/O address precluding the decoding of alias addresses every 1 KB.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.32 SNXTPTR—Subsystem ID Next Pointer Register SNXTPTR Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.2.4.33 Device: Device: Device: Device: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 41h (PCIe* MODE) 41h 41h 41h Attr Reset Value Description 7:0 RO 60h Next Ptr This field is set to 60h for the next capability list (MSI capability structure) in the chain.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.35 MSINXTPTR—MSI Next Pointer Register MSINXTPTR Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.2.4.36 Device: Device: Device: Device: 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 61h (PCIe* MODE) 61h 61h 61h Bit Attr Reset Value Description 7:0 RW-O 90h Next Ptr This field is set to 90h for the next capability list (PCI Express capability structure) in the chain.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.37 MSIMSGCTL—MSI Control Register MSIMSGCTL Bus: 0 Function: 0 Offset: 62h Bit Attr Reset Value 15:9 RV 0h Reserved 8 RO 1b Per-vector Masking Capable This bit indicates that PCI Express ports support MSI per-vector masking.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.38 MSGADR—MSI Address Register The MSI Address Register (MSIAR) contains the system specific address information to route MSI interrupts from the root ports and is broken into its constituent fields. MSGADR Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.2.4.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.41 MSIPENDING—MSI Pending Bit Register MSIPENDING Bus: 0 Bus: 0 Bus: 0 Bus: 0 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 70h (PCIe* MODE) 70h 70h 70h Reset Value 31:2 RV 0h Reserved 0h Pending Bits This field is relevant only when MSI is enabled and used for interrupts generated by the root port. When MSI is not enabled or used by the root port, this register always reads a value 0.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.44 PXPCAP—PCI Express* Capabilities Register PXPCAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Bit Attr Reset Value 15:14 RV 0h 13:9 RO 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 92h 92h 92h 92h 2 Description Reserved 00h Interrupt Message Number This field applies to root ports.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.45 DEVCAP—PCI Express* Device Capabilities Register DEVCAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 68 Device: Device: Device: Device: 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 94h 94h 94h 94h Bit Attr Reset Value 31:28 RV 0h Reserved 27:26 RO 0h Captured Slot Power Limit Scale Does not apply to root ports or integrated devices.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.
Processor Integrated I/O (IIO) Configuration Registers DEVCTRL Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 1 0 70 Device: Device: Device: Device: Device: Attr RW RW Reset Value 0 0 1 2 3 Function: Function: Function: Function: Function: 0 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: Offset: F0h (DMI2 MODE) 98h (PCIe* MODE) 98h 98h 98h Description 0b Non Fatal Error Reporting Enable This bit controls the reporting of non-fatal errors that IIO detects on the PCI Express/DMI interface.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.48 LNKCAP—PCI Express* Link Capabilities Register The Link Capabilities register identifies the PCI Express specific link capabilities. The link capabilities register needs some default values setup by the local host.
Processor Integrated I/O (IIO) Configuration Registers LNKCAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Bit 9:4 3:0 3.2.4.49 Attr RW-O RW-O 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 9Ch (PCIe* MODE) 9Ch 9Ch 9Ch Reset Value Description 4h Maximum Link Width This field indicates the maximum width of the given PCI Express Link attached to the port.
Processor Integrated I/O (IIO) Configuration Registers LNKCON Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 0 0 1 2 3 Function: Function: Function: Function: Function: 0 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: Offset: 1B0h (DMI2 MODE) A0h (PCIe* MODE) A0h A0h A0h Bit Attr Reset Value 8 RO 0b Enable Clock Power Management Not Applicable to processor 7 RW 0b Extended Synch This bit when set, forces the transmission of additional ordered sets when exiting L0s and when in recovery.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.50 LNKSTS—PCI Express* Link Status Register The PCI Express Link Status register provides information on the status of the PCI Express Link such as negotiated width, training, and so forth. The link status register needs some default values setup by the local host.
Processor Integrated I/O (IIO) Configuration Registers LNKSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 3:0 3.2.4.51 Device: Device: Device: Device: Device: Attr RO-V 0 0 1 2 3 Function: Function: Function: Function: Function: 0 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: Offset: 1B2h (DMI2 MODE) A2h (PCIe* MODE) A2h A2h A2h Reset Value Description 1h Current Link Speed This field indicates the negotiated Link speed of the given PCI Express Link. 0001 = 2.
Processor Integrated I/O (IIO) Configuration Registers SLTCAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 6 5 4 3 2 1 Datasheet, Volume 2 Device: Device: Device: Device: Attr RW-O RW-O RW-O RW-O RW-O RW-O Reset Value 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: A4h (PCIe* MODE) A4h A4h A4h Description 0b Hot-plug Capable This field defines hot-plug support capabilities for the PCI Express port.
Processor Integrated I/O (IIO) Configuration Registers SLTCAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 0 3.2.4.52 Device: Device: Device: Device: Attr RW-O 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: A4h (PCIe* MODE) A4h A4h A4h Reset Value Description 0b Attention Button Present This bit indicates that the Attention Button event signal is routed (from slot or onboard in the chassis) to the IIO’s hot-plug controller.
Processor Integrated I/O (IIO) Configuration Registers SLTCON Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 9:8 7:6 5 4 3 2 Datasheet, Volume 2 Device: Device: Device: Device: Attr RW RW RW RW RW RW 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: A8h (PCIe* MODE) A8h A8h A8h Reset Value Description 3h Power Indicator Control If a Power Indicator is implemented, writes to this field will set the Power Indicator to the written state.
Processor Integrated I/O (IIO) Configuration Registers SLTCON Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 1 0 3.2.4.53 Device: Device: Device: Device: Attr RW RW 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Reset Value Offset: Offset: Offset: Offset: A8h (PCIe* MODE) A8h A8h A8h Description 0h Power Fault Detected Enable This bit enables the generation of hot-plug interrupts or wake messages using a power fault event.
Processor Integrated I/O (IIO) Configuration Registers SLTSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 5 Attr RO 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Reset Value Offset: Offset: Offset: Offset: AAh (PCIe* MODE) AAh AAh AAh Description 0b MRL Sensor State This bit reports the status of an MRL sensor if it is implemented. 0 = MRL Closed 1 = MRL Open.
Processor Integrated I/O (IIO) Configuration Registers ROOTCON Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 2 1 82 Attr RW RW Device: Device: Device: Device: 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: ACh ACh ACh ACh Reset Value Description 0b System Error on Fatal Error Enable This field enables notifying the internal IIO core error logic of occurrence of an uncorrectable fatal error at the port or below its hierarchy.
Processor Integrated I/O (IIO) Configuration Registers ROOTCON Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 0 3.2.4.55 Attr RW Device: Device: Device: Device: 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: ACh ACh ACh ACh Reset Value Description 0b System Error on Correctable Error Enable This field controls notifying the internal IIO core error logic of the occurrence of a correctable error in the device or below its hierarchy.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.56 ROOTSTS—PCI Express* Root Status Register ROOTSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: B0h (PCIe* MODE) B0h B0h B0h Attr Reset Value 31:18 RV 0h Reserved 0b PME Pending This field indicates that another PME is pending when the PME Status bit is set.
Processor Integrated I/O (IIO) Configuration Registers DEVCAP2 Bus: 0 Bus: 0 Bus: 0 Bus: 0 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: B4h B4h B4h B4h Bit Attr Reset Value 9 RW-O 0b AtomicOp CAS Completer 128-bit Operand Supported Unsupported 8 RW-O 0b AtomicOp Completer 64-bit Operand Supported Unsupported 7 RW-O 0b AtomicOp Completer 32-bit Operand Supported Unsupported 6 RO 0b AtomicOp Routing Supported peer-to-peer routing of A
Processor Integrated I/O (IIO) Configuration Registers DEVCTRL2 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 4 3:0 3.2.4.59 Attr RW RW 0 0 1 2 3 Function: Function: Function: Function: Function: 0 0 0–1 0–3 0–3 Reset Value Offset: Offset: Offset: Offset: Offset: F8h (DMI2 MODE) B8h (PCIe* MODE) B8h B8h B8h Description 1b Completion Timeout Disable 1 = Disables the Completion Timeout mechanism for all NP tx that IIO issues on the PCIe/DMI link. 0 = Completion timeout is enabled.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.60 LNKCON2—PCI Express* Link Control 2 Register LNKCON2 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: 0 0 1 2 3 Bit Attr Reset Value 15:13 RO 0b Reserved Function: Function: Function: Function: Function: 0 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: Offset: 1C0h (DMI2 MODE) C0h (PCIe* MODE) C0h C0h C0h Description 12 RWS 0b Compliance De-emphasis This bit sets the de-emphasis level in Polling.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.61 LNKSTS2—PCI Express* Link Status Register 2 LNKSTS2 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 0 0 1 2 3 Function: Function: Function: Function: Function: 0 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: Offset: 1C2h (DMI2 MODE) C2h (PCIe* MODE) C2h C2h C2h Bit Attr Reset Value 15:6 RV 0h Reserved 5 RW1C 0b Link Equalization Request This bit is set by hardware to request Link equalization process to be performed on the link.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.62 PMCAP—Power Management Capabilities Register The PM Capabilities Register defines the capability ID, next pointer, and other power management related support. The following PM registers/capabilities are added for software compliance.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.63 PMCSR—Power Management Control and Status Register This register provides status and control information for PM events in the PCI Express port of the IIO.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.64 XPREUT_HDR_EXT—REUT PCIe* Header Extended Register XPREUT_HDR_EXT Bus: 0 Device: Bus: 0 Device: Bus: 0 Device: Bus: 0 Device: Bit 3.2.4.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.66 XPREUT_HDR_LEF—REUT Header Leaf Capability Register XPREUT_HDR_LEF Bus: 0 Device: Bus: 0 Device: Bus: 0 Device: Bus: 0 Device: 3.2.4.67 Bit Attr Reset Value 31:16 RV 0h Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 108h 108h 108h 108h Description Reserved 15:8 RO 30h LeafReutDevNum This field identifies the PCI Device/Function # where the REUT engine associated with this link resides.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.69 ACSCTRL—Access Control Services Control Register ACSCTRL Bus: 0 Bus: 0 Bus: 0 Bus: 0 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 116h(PCIe* MODE) 116h 116h 116h Attr Reset Value 15:7 RV 0h Reserved 6 RO 0b ACS Direct Translated P2P Enable Applies only to root ports This is hardwired to 0b as the component does not implement ACS Direct Translated peer-to-peer.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.71 APICLIMIT—APIC Limit Register APICLIMIT Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.2.4.72 Bit Attr Reset Value 15:12 RV 0h 11:1 RW 000h 0 RV 0h 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 142h 142h 142h 142h Description Reserved Bits 19:9 of the APIC limit Applies only to root ports. Bits 31:20 are assumed to be FECh. Bits 8:0 are a don’t care for address decode.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.74 ERRCAPHDR—PCI Express* Enhanced Capability Header Register – Root Ports ERRCAPHDR Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.2.4.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.76 UNCERRMSK—Uncorrectable Error Mask Register This register masks uncorrectable errors from being signaled.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.78 CORERRSTS—Correctable Error Status Register This register identifies the status of the correctable errors that have been detected by the PCI Express port CORERRSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: Attr Reset Value 31:14 RV 0h Reserved 13 RW1CS 0b Advisory Non-fatal Error Status Bit 3.2.4.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.82 RPERRCMD—Root Port Error Command Register This register controls behavior upon detection of errors. RPERRCMD Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.2.4.
Processor Integrated I/O (IIO) Configuration Registers RPERRSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.2.4.84 Device: Device: Device: Device: 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 178h 178h 178h 178h Bit Attr Reset Value Description 4 RW1CS 0b First Uncorrectable Fatal Set when bit 2 is set (from being clear) and the message causing bit 2 to be set is an ERR_FATAL message.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.85 PERFCTRLSTS—Performance Control and Status Register PERFCTRLSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 180h 180h 180h 180h Bit Attr Reset Value 63:42 RV 0h Reserved 41 RW 0b TLP Processing Hint Disable When set, writes or reads with TPH=1, will be treated as if TPH=0.
Processor Integrated I/O (IIO) Configuration Registers PERFCTRLSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 3.2.4.
Processor Integrated I/O (IIO) Configuration Registers MISCCTRLSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 37 36 35 34 33 104 Attr RW RWS RW RW RW Device: Device: Device: Device: 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 188h 188h 188h 188h Reset Value Description 0b Disable MCTP Broadcast to this link When set, this bit will prevent a broadcast MCTP message (w/ Routing Type of ’Broadcast from RC’) from being sent to this link.
Processor Integrated I/O (IIO) Configuration Registers MISCCTRLSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 27 RWS 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 188h 188h 188h 188h Reset Value Description 0b System Interrupt Only on Link BW/Management Status This bit, when set, will disable generating MSI and Intx interrupts on link bandwidth (speed and/or width) and management changes, even if MSI or INTx is enabled (that is, will disable generating MSI
Processor Integrated I/O (IIO) Configuration Registers MISCCTRLSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 0 1 2 3 Function: Function: Function: Function: 0 0–1 0–3 0–3 Offset: Offset: Offset: Offset: 188h 188h 188h 188h Reset Value Description 11 RWS 1b allow_1nonvc1_after_10vc1s Allow a non-VC1 request from DMI to go after every ten VC1 request (to prevent starvation of non-VC1). Notes: This bit has no effect if the port is in PCI Express mode.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.87 PCIE_IOU_BIF_CTRL—PCIe* Port Bifurcation Control Register – DMI2 Port/PCIe* PCIE_IOU_BIF_CTRL Bus: 0 Device: 0 Function: 0 Offset: 190h Bit Attr Reset Value 15:4 RV 0h Reserved 0b IOU Start Bifurcation When software writes a 1 to this bit, IIO starts the port 0 bifurcation process. After writing to this bit, software can poll the Data Link Layer link active bit in the LNKSTS register to determine if a port is up and running.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.89 PCIE_IOU_BIF_CTRL—PCIe* Port Bifurcation Control Register PCIE_IOU_BIF_CTRL Bus: 0 Device: 1 Bus: 0 Device: 2 Bus: 0 Device: 3 Offset: 190h Offset: 190h Offset: 190h Bit Attr Reset Value 15:4 RV 0h Reserved 0b Port Start Bifurcation When software writes a 1 to this bit, IIO starts the port 0 bifurcation process.
Processor Integrated I/O (IIO) Configuration Registers 3.2.4.90 PXP2CAP—Secondary PCI Express* Extended Capability Header Register PXP2CAP Bus: 0 Bus: 0 Bus: 0 Device: 1 Device: 2 Device: 3 Function: 0–1 Function: 0–3 Function: 0–3 Offset: 250h Offset: 250h Offset: 250h Bit Attr Reset Value Description 31:20 RO 280h Next Capability Offset This field contains the offset to the next PCI Express Extended Capability structure or 000h if no other items exist in the linked list of capabilities.
Processor Integrated I/O (IIO) Configuration Registers 3.2.5 PCI Express* and DMI2 Error Registers The architecture model for error logging and escalation of internal errors is similar to that of PCI Express AER, except that these internal errors never trigger an MSI and are always reported to the system software. Mask bits mask the reporting of an error and severity bit controls escalation to either fatal or non-fatal error to the internal core error logic.
Processor Integrated I/O (IIO) Configuration Registers 3.2.5.
Processor Integrated I/O (IIO) Configuration Registers 3.2.5.5 XPCORERRSTS—XP Correctable Error Status Register The contents of the next set of registers – XPCORERRSTS, XPCORERRMSK, XPUNCERRSTS, XPUNCERRMSK, XPUNCERRSEV, XPUNCERRPTR – to be defined by the design team based on microarchitecture.
Processor Integrated I/O (IIO) Configuration Registers 3.2.5.7 XPUNCERRSTS—XP Uncorrectable Error Status Register XPUNCERRSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.2.5.
Processor Integrated I/O (IIO) Configuration Registers 3.2.5.
Processor Integrated I/O (IIO) Configuration Registers 3.2.5.11 UNCEDMASK—Uncorrectable Error Detect Status Mask Register This register masks PCIe link related uncorrectable errors from causing the associated AER status bit to be set.
Processor Integrated I/O (IIO) Configuration Registers 3.2.5.13 RPEDMASK—Root Port Error Detect Status Mask Register This register masks the associated error messages (received from PCIe link and NOT the virtual ones generated internally), from causing the associated status bits in AER to be set RPEDMASK Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.2.5.
Processor Integrated I/O (IIO) Configuration Registers 3.2.5.15 XPCOREDMASK—XP Correctable Error Detect Mask Register This register masks other correctable errors from causing the associated XPCORERRSTS status bit to be set. XPCOREDMASK Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 3.2.5.
Processor Integrated I/O (IIO) Configuration Registers 3.2.5.17 XPGLBERRPTR—XP Global Error Pointer Register Check that the perfmon registers are per “cluster” XPGLBERRPTR Bus: 0 Bus: 0 Bus: 0 Bus: 0 Function: Function: Function: Function: 0 0 -1 0 -3 0–3 Offset: Offset: Offset: Offset: 232h 232h 232h 232h Attr Reset Value 15:3 RV 0h Reserved 0b XP Cluster Global First Error Pointer This field points to which of the 3 errors indicated in the XPGLBERRSTS register happened first.
Processor Integrated I/O (IIO) Configuration Registers 3.2.5.19 LER_CAP—Live Error Recovery Capability Register Live error recovery is not supported in the processor. LER_CAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.2.5.
Processor Integrated I/O (IIO) Configuration Registers 3.2.5.22 LER_UNCERRMSK—Live Error Recovery Uncorrectable Error Mask Register This register masks uncorrectable errors from being signaled as LER events.
Processor Integrated I/O (IIO) Configuration Registers 3.2.5.
Processor Integrated I/O (IIO) Configuration Registers LN[0:3]EQ Bus: 0 Bus: 0 Bus: 0 3.2.6.2 Device: 1 Device: 2 Device: 3 Function: 0–1 Function: 0–3 Function: 0–3 Offset: 25Ch, 25Eh, 260h, 262h Offset: 25Ch, 25Eh, 260h, 262h Offset: 25Ch, 25Eh, 260h, 262h Bit Attr Reset Value 7 RV 0h Reserved 6:4 RO 7h Upstream Component Receiver Preset Hint Receiver Preset Hint for Upstream Component. The upstream component uses this hint for receiver equalization. The Root Ports are upstream components.
Processor Integrated I/O (IIO) Configuration Registers LN[4:7]EQ Bus: 0 Bus: 0 Bus: 0 Bit Attr Device: 1 Device: 2 Device: 3 Reset Value Function: 0 Function: 0, 2 Function: 0, 2 Offset: 264h, 266h, 268h, 26Ah Offset: 264h, 266h, 268h, 26Ah Offset: 264h, 266h, 268h, 26Ah Description 10:8 RW-O 2h Downstream Component Transmitter Preset Transmitter Preset for Downstream Component with the following encoding. The Upstream component must pass on this value in the EQ TS2’es.
Processor Integrated I/O (IIO) Configuration Registers 3.2.6.3 LN[8:15]EQ—Lane 8 though Lane 15 Equalization Control Register This register is unused when the link is configured at x4 or x8 in the bifurcation register.
Processor Integrated I/O (IIO) Configuration Registers LN[8:15]EQ Bus: 0 Device: 2 Bus: 0 Device: 3 Bit 2:0 Attr RW-O Function: 0 Function: 0 Offset: 26Ch, 26Eh, 270h, 272h, 274h, 276h, 278h, 278h Offset: 26Ch, 26Eh, 270h, 272h, 274h, 276h, 278h, 278h Reset Value 2h Description Upstream Component Transmitter Preset Transmitter Preset for an Upstream Component. The Root Ports are upstream components. The encodings are defined below. 000b = -6 dB for de-emphasis, 0 dB for preshoot 001b = -3.
Processor Integrated I/O (IIO) Configuration Registers 3.2.7.3 XPPMDH—XP PM Data High Bits Register This register contains the high nibbles from each of the PMD 36-bit counter register. XPPMDH Bus: 0 Bus: 0 Bus: 0 3.2.7.4 Device: 0 Device: 2 Device: 3 Function: 0 Function: 0 Function: 0 Offset: 490 Offset: 490 Offset: 490 Bit Attr Reset Value 15:12 RV 0h Reserved 11:8 RW-V 0h High Nibble PEX Counter1 value High order bits [35:32] of the 36-bit PM Data1 register.
Processor Integrated I/O (IIO) Configuration Registers 3.2.7.5 XPPMR[0:1]—XP PM Response Control Register The PMR register controls operation of its associated counter, and provides overflow or max compare status information. XPPMR[0:1] Bus: 0 Bus: 0 Bus: 0 Device: 0 Device: 2 Device: 3 Function: 0 Function: 0 Function: 0 Offset: 494, 498 Offset: 494, 498 Offset: 494, 498 Bit Attr Reset Value 31 RV 0h Reserved 0b Not greater than comparison 0 = PMC will compare a greater than function.
Processor Integrated I/O (IIO) Configuration Registers XPPMR[0:1] Bus: 0 Bus: 0 Bus: 0 Bit 15:14 13:11 10:8 128 Attr RW RW RW Device: 0 Device: 2 Device: 3 Function: 0 Function: 0 Function: 0 Offset: 494, 498 Offset: 494, 498 Offset: 494, 498 Reset Value Description 00b Count Mode This field sets how the events will be counted. 00 = Count clocks when event is logic high. Counting is level sensitive, whenever the event is logic 1 the counter is enabled to count. 01 = Count rising edge events.
Processor Integrated I/O (IIO) Configuration Registers XPPMR[0:1] Bus: 0 Bus: 0 Bus: 0 Bit Offset: 494, 498 Offset: 494, 498 Offset: 494, 498 Description Compare Mode This field defines how the PMC (compare) register is to be used. 00 = compare mode disabled (PMC register not used) 01 = max compare only: The PMC register value is compared with the counter value. If the counter value is greater then the Compare Status (CMPSTAT) will be set.
Processor Integrated I/O (IIO) Configuration Registers 3.2.7.6 XPPMEVL[0:1]—XP PM Events Low Register Selections in this register correspond to fields within the PCIe header. Each field selection is logically combined according to the match equation. The qualifications for fields in this register are listed below. It should be noted that the bit selections are generic for packet and for either inbound or outbound direction. Because of this, there will be bit fields that do not make sense.
Processor Integrated I/O (IIO) Configuration Registers XPPMEVL[0:1] Bus: 0 Bus: 0 Bus: 0 Bit 27:26 25:24 23:22 21:20 19:18 17:16 15:11 10:4 3:0 Datasheet, Volume 2 Attr RW RW RW RW RW RW RW RW RW Device: 0 Device: 2 Device: 3 Function: 0 Function: 0 Function: 0 Reset Value Offset: 49C, 4A0 Offset: 49C, 4A0 Offset: 49C, 4A0 Description 0b Request or Completion Packet Selection x1 = Request packet 1x = Completion packet 11 = Either 0b Read or Write Selection x1 = Read 1x = Write
Processor Integrated I/O (IIO) Configuration Registers 3.2.7.7 XPPMEVH[0:1]—XP PM Events High Register Selections in this register correspond to fields within the PEX packet header. Each field selection is ANDed with all other fields in this register including the XPPMEVL except for the Global Event signals. These signals are OR’ed with any event in the XPPMEVL and enables for debug operations requiring the accumulation of specific debug signals.
Processor Integrated I/O (IIO) Configuration Registers 3.2.7.8 XPPMER[0:1]—XP PM Resource Events Register This register is used to select queuing structures for measurement. Use of this event register is mutually exclusive with the XPPMEV{L,H} registers. The Event Register Select field in the PMR register must select this register for to enable monitoring operations of the queues.
Processor Integrated I/O (IIO) Configuration Registers 3.2.8 DMI Root Complex Register Block (RCRB) This block is mapped into memory space, using register DMIRCBAR [Device 0:Function 0, offset 50h]. Table 3-8.
Processor Integrated I/O (IIO) Configuration Registers 3.2.8.1 DMIVC0RCAP—DMI VC0 Resource Capability Register DMIVC0RCAP Bus: 0 3.2.8.2 Device: 0 Offset: 10 Bit Attr Reset Value 31:16 RO 0000h Function: 0 MMIO BAR: DMIRCBAR Description Max Time Slots 15 RO 0h Reject Snoop Transactions 0 = Transactions with or without the No Snoop bit set within the TLP header are allowed on this VC.
Processor Integrated I/O (IIO) Configuration Registers 3.2.8.3 DMIVC0RSTS—DMI VC0 Resource Status Register Reports the Virtual Channel specific status. DMIVC0RSTS Bus: 0 3.2.8.4 Bit Attr Reset Value 15:2 RV 0h Reserved Function: 0 MMIO BAR: DMIRCBAR Description 1 RO-V 1b Virtual Channel 0 Negotiation Pending 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling).
Processor Integrated I/O (IIO) Configuration Registers 3.2.8.5 DMIVC1RCTL—DMI VC1 Resource Control Register Controls the resources associated with PCI Express* Virtual Channel 1. DMIVC1RCTL Bus: 0 Bit Attr Device: 0 Offset: 20 Function: 0 MMIO BAR: DMIRCBAR Reset Value Description 31 RW-LB 0b Virtual Channel 1 Enable 0 = Virtual Channel is disabled. 1 = Virtual Channel is enabled. See exceptions below.
Processor Integrated I/O (IIO) Configuration Registers 3.2.8.6 DMIVC1RSTS—DMI VC1 Resource Status Register Reports the Virtual Channel specific status. DMIVC1RSTS Bus: N 3.2.8.7 Bit Attr Reset Value 15:2 RV 0h Reserved Function: 0 MMIO BAR: DMIRCBAR Description 1 RO-V 1b Virtual Channel 1 Negotiation Pending 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling).
Processor Integrated I/O (IIO) Configuration Registers 3.2.8.8 DMIVCPRCTL—DMI VCP Resource Control Register Controls the resources associated with the DMI Private Channel (VCp). DMIVCPRCTL Bus: 0 Bit Attr Device: 0 Offset: 2C Function: 0 MMIO BAR: DMIRCBAR Reset Value Description 31 RW-LB 0b Virtual Channel Private Enable 0 = Virtual Channel is disabled. 1 = Virtual Channel is enabled. See exceptions below.
Processor Integrated I/O (IIO) Configuration Registers 3.2.8.9 DMIVCPRSTS—DMI VCP Resource Status Register Reports the Virtual Channel specific status. DMIVCPRSTS Bus: N 3.2.8.10 Bit Attr Reset Value 15:2 RV 0h Reserved Function: 0 MMIO BAR: DMIRCBAR Description 1 RO-V 1b Virtual Channel Private Negotiation Pending 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling).
Processor Integrated I/O (IIO) Configuration Registers 3.2.8.11 DMIVCMRCTL—DMI VCM Resource Control Register Controls the resources associated with PCI Express Virtual Channel 0. DMIVCMRCTL Bus: 0 Bit 3.2.8.12 Attr Device: 0 Offset: 38 Function: 0 MMIO BAR: DMIRCBAR Reset Value Description 31 RW-LB 0b Virtual Channel M Enable 0 = Virtual Channel is disabled. 1 = Virtual Channel is enabled. See exceptions below.
Processor Integrated I/O (IIO) Configuration Registers 3.2.8.13 DMIRCLDECH—DMI Root Complex Link Declaration Register This register only has meaning if placed in the configuration space. DMIRCLDECH Bus: 0 3.2.8.14 Bit Attr Reset Value 31:20 RO 080h 19:16 RO 1h 15:0 RO 0005h MMIO BAR: DMIRCBAR Description Pointer to Next Capability Capability Version Indicates capability structure version Extended Capability ID Indicates Root Complex Link Declaration capability structure.
Processor Integrated I/O (IIO) Configuration Registers 3.2.8.16 DMILBA0—DMI Link Address Register DMILBA0 Bus: 0 3.2.8.17 Device: 0 Offset: 58 Bit Attr Reset Value 31:12 RW-O 00000h 11:0 RV 0h MMIO BAR: DMIRCBAR Description Link Address Reserved DMIVC1CdtThrottle—DMI VC1 Credit Throttle Register DMIVC1CdtThrottle Bus: 0 Device: 0 Offset: 60 3.2.8.
Processor Integrated I/O (IIO) Configuration Registers 3.2.8.19 DMIVCmCdtThrottle—DMI VCm Credit Throttle Register DMIVCmCdtThrottle Bus: 0 Device: 0 Offset: 68 144 Function: 0 MMIO BAR: DMIRCBAR Bit Attr Reset Value 31:24 RWS 00h 23:22 RV 0h 21:16 RWS 00h Posted Request Header VCm Credit Withhold Number of VCm Posted Request credits to withhold from being reported or used.
Processor Integrated I/O (IIO) Configuration Registers 3.3 Integrated I/O Core Registers This section describes the standard PCI configuration registers and device specific Configuration Registers related to below: • Intel VT-d, address mapping, system management and Miscellaneous Registers – Device 5, Function 0 • IIO control/status and Global Error Registers- Device 5, Function 2 • IOxAPIC Registers- Device 5, Function 4 3.3.1 Configuration Register Maps (Device 5, Function: 0, 2 and 4) Table 3-9.
Processor Integrated I/O (IIO) Configuration Registers Table 3-10.
Processor Integrated I/O (IIO) Configuration Registers Table 3-11.
Processor Integrated I/O (IIO) Configuration Registers Table 3-12.
Processor Integrated I/O (IIO) Configuration Registers Table 3-13.
Processor Integrated I/O (IIO) Configuration Registers Table 3-14.
Processor Integrated I/O (IIO) Configuration Registers Table 3-15.
Processor Integrated I/O (IIO) Configuration Registers Table 3-16.
Processor Integrated I/O (IIO) Configuration Registers Table 3-17.
Processor Integrated I/O (IIO) Configuration Registers Table 3-18.
Processor Integrated I/O (IIO) Configuration Registers 3.3.2 PCI Configuration Space Registers Common to Device 5 3.3.2.1 VID—Vendor Identification Register VID Bus: 0 3.3.2.2 Device: 5 Bit Attr Reset Value 15:0 RO 8086h Offset: 00h Description Vendor Identification Number The value is assigned by PCI-SIG to Intel. DID—Device Identification Register DID Bus: 0 Bit 15:0 3.3.2.
Processor Integrated I/O (IIO) Configuration Registers PCICMD Bus: 0 3.3.2.4 Device: 5 Function: 0,2,4 Offset: 04h Bit Attr Reset Value 3 RO 0b Special Cycle Enable Not applicable. Hardwired to 0.
Processor Integrated I/O (IIO) Configuration Registers 3.3.2.5 RID—Revision Identification Register This register contains the revision number of the Integrated I/O. RID Bus: 0 Bit 7:0 3.3.2.6 Device: 5 Attr RO Function: 0,2,4 Offset: 08h Reset Value Description 00h Revision_ID Reflects the Uncore Revision ID after reset. Reflects the Compatibility Revision ID after BIOS writes 69h to any RID register in any processor function.
Processor Integrated I/O (IIO) Configuration Registers 3.3.2.8 HDR—Header Type Register This register identifies the header layout of the configuration space. HDR Bus: 0 Bit Attr Reset Value Description RO 1b 6:0 RO 00h Configuration Layout This field identifies the format of the configuration header layout. It is Type 0 for all these devices. The default is 00h, indicating a ’endpoint device’. 1b Multi-function Device This bit defaults to 1b since all these devices are multi-function.
Processor Integrated I/O (IIO) Configuration Registers 3.3.2.11 CAPPTR—Capability Pointer Register The CAPPTR provides the offset to the location of the first device capability in the capability list. CAPPTR Bus: 0 3.3.2.12 Device: 5 Bit Attr Reset Value 7:0 RO Dev 5, F 0,2 = 40h Dev 5, F4 = 44h Function: 0,2,4 Offset: 34h Description Capability Pointer Points to the first capability structure for the device which is the PCIe capability.
Processor Integrated I/O (IIO) Configuration Registers 3.3.2.15 PXPNXTPTR—PCI Express* Next Pointer Register The PCI Express Capability List register enumerates the PCI Express Capability structure in the PCI 3.0 configuration space. PXPNXTPTR Bus: 0 3.3.2.16 Device: 5 Bit Attr Reset Value 7:0 RO E0h Function: 0,2 Offset: 41h Description Next Ptr This field is set to the PCI PM capability.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.2 MMCFG—MMCFG Address Range Register MMCFG Bus: 0 Bit 3.3.3.3 Device: 5 Attr Reset Value Offset: 84 Description MMCFG Limit Address This field indicates the limit address which is aligned to a 64 MB boundary. Any access that decodes to be between MMCFG.BASE Addr MMCFG.LIMIT targets the MMCFG region and is aborted by IIO. Setting the MMCFG.BASE greater than MMCFG.LIMIT disables this region.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.5 GENPROTRANGE1_LIMIT—Generic Protected Memory Range 1 Limit Address Register GENPROTRANGE1_LIMIT Bus: 0 Device: 5 3.3.3.6 Bit Attr Reset Value 63:51 RV 0h 50:16 RW-LB 000000 000h 15:0 RV 0h Offset: B8 Description Reserved Limit address This field indicates bits 50:16 of the generic memory address range that needs to be protected from inbound DMA accesses.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.7 GENPROTRANGE2_LIMIT—Generic Protected Memory Range 2 Limit Address Register GENPROTRANGE2_LIMIT Bus: 0 Device: 5 3.3.3.8 Bit Attr Reset Value 63:51 RV 0h 50:16 RW-LB 000000 000h 15:0 RV 0h Offset: C8 Description Reserved Limit address This field indicates bits 50:16 of the generic memory address range that needs to be protected from inbound DMA accesses.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.10 NCMEM_BASE—NCMEM Base Register NCMEM_BASE Bus: 0 Bit 3.3.3.11 Attr 63:26 RW-LB 25:0 RV Bit Reset Value Offset: E0 Description Non Coherent memory base address This field describes the base address of a 64 MB aligned DRAM memory region on Intel QPI that is non-coherent. Address bits 63:26 of an inbound address if it satisfies ’NcMem.Base[63:26] A[63:26] NcMem.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.13 MENCMEM_LIMIT—Intel® ME Non-coherent Memory Limit Address Register MENCMEM_LIMIT Bus: 0 Device: 5 Bit 3.3.3.14 Attr Function: 0 Offset: F8 Reset Value Description Intel ME UMA Limit Address This field indicates the limit address which is aligned to a 1 MB boundary. Bits [63:19] corresponds to A[63:19] address bits. Any address that falls within MENCMEMBASE Addr MENCMEMLIMIT range is considered to target the UMA range.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.15 LMMIOL—Local MMIO Low Base Register LMMIOL Bus: 0 Bit 3.3.3.16 Device: 5 Attr Reset Value 31:24 RW-LB 00h 23:16 RV 0h 15:8 RW-LB 00h 7:0 RV 0h Offset: 10C Description Local MMIO Low Limit Address This field corresponds to A[31:24] of MMIOL limit.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.17 LMMIOH_LIMIT—Local MMIO High Base Register LMMIOH_LIMIT Bus: N 3.3.3.18 Device: 5 Bit Attr Reset Value 63:51 RV 0h 50:26 RW-LB 000000 0h 25:0 RV 0h Function: 0 Offset: 118 Description Reserved Local MMIOH Limit Address This field corresponds to A[50:26] of MMIOH limit.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.19 GENPROTRANGE0_LIMIT—Generic Protected Memory Range 0 Limit Address Register GENPROTRANGE0_LIMIT Bus: 0 Device: 5 3.3.3.20 Bit Attr Reset Value 63:51 RV 0h 50:16 RW-LB 000000 000h 15:0 RV 0h Offset: 128 Description Reserved Limit Address This field indicates bits 50:16 of generic memory address range that needs to be protected from inbound DMA accesses.
Processor Integrated I/O (IIO) Configuration Registers CIPCTRL Bus: 0 Bit 11:9 8:6 Device: 5 Attr RW RW Function: 0 Offset: 140 Reset Value Description 0h RRB Size (Write Cache Size) Specifies the number of entries used in each half of the write cache. The default is to use all entries.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.21 CIPSTS—Coherent Interface Protocol Status Register CIPSTS Bus: 0 Offset: 144 Attr Reset Value 31:3 RV 0h Reserved 1b RRB non-phold_arb Empty This indicates that there are no pending requests in the RRB with the exception of ProcLock/Unlock* messages to the lock arbiter. 0 = Pending RRB requests 1 = RRB Empty except for any pending Proclock*/Unlock This is a live bit and hence can toggle clock by clock.
Processor Integrated I/O (IIO) Configuration Registers CIPDCASAD Bus: 0 Device: 5 Bit Attr Reset Value 10:8 RW 000b 7:1 RV 0h 0 RW 0b Function: 0 Offset: 148 Description DCA Lookup Table Entry 0 For a TPH/DCA request, this field specifies the target NodeID[2:0] when the inverted Tag[2:0] is 0. Reserved Enable TPH/DCA When disabled, PrefetchHint will not be sent on the coherent interface.
Processor Integrated I/O (IIO) Configuration Registers CIPINTRC Bus: 0 3.3.3.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.25 VTBAR—Base Address Register for Intel® VT-d Registers VTBAR Bus: 0 Function: 0 Offset: 180 Bit Attr Reset Value 31:13 RW-LB 00000h 12:1 RV 0h Reserved 0b Intel VT-d Base Address Enable Accesses to registers pointed to by VTBAR are accessible using message channel or JTAG mini-port, irrespective of the setting of this enable bit.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.27 VTISOCHCTRL—Intel® VT-d Isoch Related Control Register VTISOCHCTRL Bus: 0 Function: 0 Offset: 188 Bit Attr Reset Value 31:9 RV 0h Reserved 0b Intel High Definition Audio traffic to use VCp channel 1 = all VCp traffic uses the Intel High Definition Audio optimizations in Intel VT-d pagewalk request. 0 = non-Intel High Definition Audio VCp traffic uses VC0 channel for Intel VT-d pagewalk request.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.28 VTGENCTRL2—Intel® VT-d General Control 2 Register VTGENCTRL2 Bus: 0 Device: 5 Function: 0 Offset: 18C Bit Attr Reset Value 31:12 RV 0h Reserved 0b LRU Count Control This bit controls what increments the LRU counter that is used to degrade the LRU bits in the IOTLB, L1/L2, and L3 caches. 1 = Count Cycles (same as TB) 0 = Count Requests 7h LRU Timer This bit controls the rate at which the LRU buckets should degrade.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.29 IOTLBPARTITION—IOTLB Partitioning Control Register IOTLBPARTITION Bus: 0 Device: 5 Bit 3.3.3.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.31 VTUNCERRMSK—Intel® VT Uncorrectable Error Mask Register VTUNCERRMSK Bus: 0 3.3.3.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.33 VTUNCERRPTR—Intel® VT Uncorrectable Error Pointer Register VTUNCERRPTR Bus: 0 Bit Attr Reset Value 7:5 RV 0h 4:0 3.3.3.34 ROS-V 00h Function: 0 Offset: 1B4 Description Reserved Intel VT Uncorrectable First Error Pointer This field points to which of the unmasked uncorrectable errors happened first.
Processor Integrated I/O (IIO) Configuration Registers IIOMISCCTRL Bus: 0 Device: 5 Bit Attr Reset Value 36:35 RV 0h Function: 0 Offset: 1C0 Description Reserved Show the PCI Express Port identifier in Intel QPI packets A Port Identifier that identifies which PCI Express port a transaction comes from will be placed in the AD Ring TNID[2:0] field of the request packet, when enabled. This field is normally used for DCAHint and is not used for normal demand read.
Processor Integrated I/O (IIO) Configuration Registers IIOMISCCTRL Bus: 0 Bit Reset Value Function: 0 Offset: 1C0 Description 24 RW 0b Disable all allocating flows When this bit is set, IIO will no more issue any new inbound IDI command that can allocate into LLC. Instead, all the writes will use one of the non-allocating commands – PCIWiL/PCIWiLF/PCINSWr/PCINSWrF. This is provided primarily for PSMI where a mode is needed to not allocate into the LLC.
Processor Integrated I/O (IIO) Configuration Registers IIOMISCCTRL Bus: 0 Function: 0 Offset: 1C0 Bit Attr Reset Value Description 14 RW 0b Pipeline Non-Snooped Writes on the Coherent Interface When this bit is set, it allows inbound non-snooped writes to pipeline at the coherent interface; issuing the writes before previous writes are completed in the coherent domain.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.35 IRP_MISC_DFX0—Coherent Interface Miscellaneous DFx 0 Register IRP_MISC_DFX0 Bus: 0 Device: 5 Offset: 800 Bit Attr Reset Value 31 RW-L 0b Disable Prefetch Ack Bypass Path A bypass path for the pf_ack reduces latency by 3 cycles. This bit disables the bypass.
Processor Integrated I/O (IIO) Configuration Registers IRP_MISC_DFX0 Bus: 0 Device: 5 Bit 3.3.3.36 Attr Function: 0 Offset: 800 Reset Value Description Minimum Free Conflict Queue Entries The number of free conflict entries at which the non-isoc transactions are throttled. There are a total of 32 entries to begin with. Note: Locked by DBGBUSLCK 13:9 RW-L 09h 8 RW-L 1b Check IO Config Format Does some format checking (address alignment) for io and cfg transactions.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.37 IRP0DELS—Coherent Interface 0 Debug Event Lane Select Register IRP0DELS Bus: 0 3.3.3.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.39 IRP0DBGRING[0:1]—Coherent Interface 0 Debug Ring 0 Register IRP0DBGRING[0:1] Bus: 0 Device: 5 3.3.3.40 Bit Attr Reset Value 63:0 RO 000000 000000 0000h Debug Ring Signal IRP1DBGRING[0:1]—Coherent Interface 1 Debug Ring 0 Register Bit Attr Reset Value 63:0 RO 000000 000000 0000h Function: 0 Offset: 820 Description Debug Ring Signal IRP0DBGRING1—Coherent Interface 0 Debug Ring 1 Register IRP0DBGRING1 Bus: 0 3.3.3.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.43 IRP0RNG—Coherent Interface 0 Cluster Debug Ring Control Register IRP0RNG Bus: 0 Bit 31 30:27 26:24 23:21 20:18 17:15 186 Attr RWS-L RWS-L RWS-L RWS-L RWS-L RWS-L Device: 5 Reset Value 0b 0000b Function: 0 Offset: 830 Description Select Trigger This bit selects the cluster trigger output signals (ClusterTrigOut[1:0]) from this cluster and places them onto the two LSBs of the lane selected by primary lane (bits 30:27).
Processor Integrated I/O (IIO) Configuration Registers IRP0RNG Bus: 0 Bit 14:12 11:9 8:6 5:3 2:0 Datasheet, Volume 2 Attr RWS-L RWS-L RWS-L RWS-L RWS-L Device: 5 Reset Value Function: 0 Offset: 830 Description 000b Debug ring source lane 4 select This field selects the source of data to be driven to the next cluster on lane 4.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.44 IRP1RNG—Coherent Interface 1 Cluster Debug Ring Control Register IRP1RNG Bus: 0 Bit 31 30:27 26:24 23:21 20:18 17:15 188 Attr RWS-L RWS-L RWS-L RWS-L RWS-L RWS-L Device: 5 Reset Value 0b 0000b Function: 0 Offset: 834 Description Select Trigger This bit selects the cluster trigger output signals (ClusterTrigOut[1:0]) from this cluster and places them onto the two LSBs of the lane selected by primary lane (bits 30:27).
Processor Integrated I/O (IIO) Configuration Registers IRP1RNG Bus: 0 Bit 14:12 11:9 8:6 5:3 2:0 Datasheet, Volume 2 Attr RWS-L RWS-L RWS-L RWS-L RWS-L Device: 5 Reset Value Function: 0 Offset: 834 Description 000b Debug ring source lane 4 select This field selects the source of data to be driven to the next cluster on lane 4.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.45 IRPEGCREDITS—R2PCIe Egress Credits Register This register specifies the Credits used by IRP when transmitting messages to various destinations on various rings. BIOS should leave this register at default unless noted otherwise in the individual bit descriptions. These registers are made CSR only for the scenario that this might be needed for testing purposes.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4 Global System Control and Error Registers 3.3.4.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.2 IIOERRSV—IIO Core Error Severity Register This register associates the detected IIO internal core errors to an error severity level. An individual error is reported with the corresponding severity in this register. Software can program the error severity to one of the three severities supported by IIO. This register is sticky and can only be reset by PWRGOOD. IIOERRSV Bus: 0 Bit Attr Reset Value 31:14 RV 0h 13:12 11:10 3.3.4.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.4 PCIERRSV—PCIe* Error Severity Map Register This register allows remapping of the PCIe errors to the IIO error severity. PCIERRSV Bus: 0 Bit Attr Reset Value 31:6 RV 0h 5:4 3:2 1:0 3.3.4.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.6 VIRAL—Viral Alert Register This register provides the option to generate viral alert upon the detection of fatal error. Viral is not officially supported in the processor but am still leaving it in here because IVB might need it. VIRAL Bus: 0 3.3.4.7 Device: 5 Bit Attr Reset Value 31:3 RV 0h Reserved Function: 2 Offset: A0 Description 2 RWS 0b Fatal Viral Alert Enable This bit enables viral alert for Fatal Error.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.8 ERRPINST—Error Pin Status Register This register reflects the state of the error pin assertion. The status bit of the corresponding error pin is set upon the deassertion to assertion transition of the error pin. This bit is cleared by the software with writing 1 to the corresponding bit. ERRPINST Bus: 0 3.3.4.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.10 VPPCTL—VPP Control Register This register defines the control/command for PCA9555.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.12 GNERRST—Global Non-Fatal Error Status Register This register indicates the non-fatal error reported to the IIO global error logic. An individual error status bit that is set indicates that a particular local interface has detected an error.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.13 GFERRST—Global Fatal Error Status Register This register indicates the fatal error reported to the IIO global error logic. An individual error status bit that is set indicates that a particular local interface has detected an error. GFERRST Bus: 0 Function: 2 Offset: 1C4 Bit Attr Reset Value 31:26 RV 0h Reserved 25 RW1CS 0b Intel VT-d Error Status This register indicates the fatal error reported to the Intel VT-d error logic.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.14 GERRCTL—Global Error Control Register This register controls/masks the reporting of errors detected by the IIO local interfaces. An individual error control bit that is set masks error reporting of the particular local interface; software may set or clear the control bit. This register is sticky and can only be reset by PWRGOOD. Note that bit fields in this register can become reserved depending on the port configuration.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.15 GSYSST—Global System Event Status Register This register indicates the error severity signaled by the IIO global error logic. Setting of an individual error status bit indicates that the corresponding error severity has been detected by the IIO. GSYSST Bus: 0 3.3.4.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.18 GFNERRST—Global Fatal NERR Status Register GFNERRST Bus: 0 3.3.4.19 Bit Attr Reset Value 31:27 RV 0h 26:0 ROS-V 000000 0h Function: 2 Offset: 1E8 Description Reserved Global Error Status Log This filed logs the global error status register content when the next fatal error is reported. This has the same format as the global error status register (GFERRST).
Processor Integrated I/O (IIO) Configuration Registers 3.3.5 Local Error Registers 3.3.5.1 IRPP0ERRST—IRP Protocol Error Status Register This register indicates the error detected by the Coherent Interface. IRPP0ERRST Bus: 0 3.3.5.2 Device: 5 Function: 2 Offset: 230 Bit Attr Reset Value 31:15 RV 0h Reserved 14 RW1CS 0b Protocol Parity Error (DB) This bit was originally used for detecting parity error on coherent interface; however, no parity checks exist.
Processor Integrated I/O (IIO) Configuration Registers IRPP0ERRCTL Bus: 0 3.3.5.
Processor Integrated I/O (IIO) Configuration Registers 3.3.5.4 IRPP0FNERRST—IRP Protocol Fatal NERR Status Register The error status log indicates which error is causing the report of the next fatal error event (any event that is not the first). IRPP0FNERRST Bus: 0 3.3.5.5 Device: 5 Offset: 23C Bit Attr Reset Value 31:15 RV 0h Reserved 14 ROS-V 0b Protocol Parity Error (DB) This bit was originally used for detecting parity error on coherent interface; however, no parity checks exist.
Processor Integrated I/O (IIO) Configuration Registers 3.3.5.6 IRPP0NFERRST—IRP Protocol Non-Fatal FERR Status Register The error status log indicates which error is causing the report of the first non-fatal error event. IRPP0NFERRST Bus: 0 3.3.5.7 Device: 5 Function: 2 Offset: 250 Bit Attr Reset Value 31:15 RV 0h Reserved 14 ROS-V 0b Protocol Parity Error (DB) This bit was originally used for detecting parity error on coherent interface; however, no parity checks exist.
Processor Integrated I/O (IIO) Configuration Registers IRPP0NNERRST Bus: 0 3.3.5.8 Device: 5 Attr Reset Value 1 ROS-V 0b Write Cache Correctable ECC (B4) A single bit ECC error was detected and corrected within the Write Cache.
Processor Integrated I/O (IIO) Configuration Registers 3.3.5.11 IRPP1ERRST—IRP Protocol Error Status Register This register indicates the error detected by the Coherent Interface. IRPP1ERRST Bus: 0 Device: 5 Bit Attr Reset Value 31:15 RV 0h Reserved Function: 2 Offset: 2B0 Description 14 RW1CS 0b Protocol Parity Error (DB) This bit was originally used for detecting parity error on coherent interface; however, no parity checks exist.
Processor Integrated I/O (IIO) Configuration Registers 3.3.5.12 IRPP1ERRCTL—IRP Protocol Error Control Register This register enables the error status bit setting for a Coherent Interface detected error. Setting of the bit enables the setting of the corresponding error status bit in IRPPERRST register. If the bit is cleared, the corresponding error status will not be set.
Processor Integrated I/O (IIO) Configuration Registers 3.3.5.13 IRPP1FFERRST—IRP Protocol Fatal FERR Status Register The error status log indicates which error is causing the report of the first fatal error event. IRPP1FFERRST Bus: 0 3.3.5.14 Device: 5 Function: 2 Offset: 2B8 Bit Attr Reset Value 31:15 RV 0h Reserved 14 ROS-V 0b Protocol Parity Error (DB) This bit was Originally used for detecting parity error on coherent interface; however, no parity checks exist.
Processor Integrated I/O (IIO) Configuration Registers IRPP1FNERRST Bus: 0 3.3.5.15 Device: 5 Offset: 2BC Bit Attr Reset Value 1 ROS-V 0b Write Cache Correctable ECC (B4) A single bit ECC error was detected and corrected within the Write Cache. 0 RV 0h Reserved Description IRPP1FFERRHD[0:3]—IRP Protocol Fatal FERR Header Log 0 Register IRPP1FFERRHD[0:3] Bus: 0 Device: 5 3.3.5.
Processor Integrated I/O (IIO) Configuration Registers 3.3.5.17 IRPP1NNERRST—IRP Protocol Non-Fatal NERR Status Register The error status log indicates which error is causing the report of the next non-fatal error event (any event that is not the first). IRPP1NNERRST Bus: 0 3.3.5.
Processor Integrated I/O (IIO) Configuration Registers 3.3.5.20 IRPP1ERRCNT—IRP Protocol Error Counter Register IRPP1ERRCNT Bus: 0 Function: 2 Offset: 2EC Bit Attr Reset Value 31:8 RV 0h Reserved 7 RW1CS 0b Error Accumulator Overflow 0 = No overflow occurred 1 = Error overflow. The error count may not be valid. 6:0 3.3.5.
Processor Integrated I/O (IIO) Configuration Registers 3.3.5.23 IIOFFERRST—IIO Core Fatal FERR Status Register IIOFFERRST Bus: 0 Bit Attr Reset Value 31:7 RV 0h 6:0 3.3.5.24 Device: 5 ROS-V 00h Function: 2 Offset: 308 Description Reserved IIO Core Error Status Log The error status log indicates which error is causing the report of the first error event. The encoding indicates the corresponding bit position of the error in the error status register.
Processor Integrated I/O (IIO) Configuration Registers 3.3.5.27 IIONFERRHD[0:3]—IIO Core Non-Fatal FERR Header Register Header log stores the IIO data path header information of the associated IIO core error. The header indicates where the error is originating from and the address of the cycle. IIONFERRHD[0:3] Bus: 0 Device: 5 3.3.5.
Processor Integrated I/O (IIO) Configuration Registers 3.3.5.30 IIOERRCNT—IIO Core Error Counter Register IIOERRCNT Bus: 0 Offset: 340 Attr Reset Value 31:8 RV 0h Reserved 7 RW1CS 0b Error Accumulator Overflow 0 = No overflow occurred 1 = Error overflow. The error count may not be valid. RW1CS 00h Description Error Accumulator This counter accumulates errors that occur when the associated error type is selected in the ERRCNTSEL register. Notes: 1. This register is cleared by writing 7Fh.
Processor Integrated I/O (IIO) Configuration Registers 3.3.5.33 MIFFERRST—Miscellaneous Fatal First Error Status Register MIFFERRST Bus: 0 Bit 3.3.5.
Processor Integrated I/O (IIO) Configuration Registers 3.3.5.37 MINFERRHDR_[0:3]—Miscellaneous Non-Fatal First Error Header 0 Log Register MINFERRHDR_[0:3] Bus: 0 Device: 5 3.3.5.38 Bit Attr Reset Value 31:0 ROS-V 000000 00h Description Header Device: 5 Bit Attr Reset Value 31:11 RV 0h 10:0 ROS-V 000h Function: 2 Offset: 3B4 Description Reserved Miscellaneous Error Status Log MIERRCNTSEL—Miscellaneous Error Count Select Register MIERRCNTSEL Bus: 0 Bit 3.3.5.
Processor Integrated I/O (IIO) Configuration Registers 3.3.6 IOxAPIC PCI Configuration Space This section covers the I/OxAPIC related registers 3.3.6.1 MBAR—IOxAPIC Base Address Register MBAR Bus: 0 Bit 3.3.6.2 Device: 5 Attr Reset Value Description 31:12 RW 0h 11:4 RO 0h Reserved 3 RO 0b Prefetchable The IOxAPIC registers are not prefetchable. 2:1 RO 00b 0 RO 0b Type The IOAPIC registers can only be placed below 4G system address space.
Processor Integrated I/O (IIO) Configuration Registers 3.3.6.4 INTL—Interrupt Line Register INTL Bus: 0 3.3.6.5 Device: 5 Bit Attr Reset Value 7:0 RO 00h Offset: 3C Description Interrupt Line Not applicable for these devices INTPIN—Interrupt Pin Register - Others INTPIN Bus: 0 3.3.6.
Processor Integrated I/O (IIO) Configuration Registers 3.3.6.7 PMCAP—Power Management Capabilities Register PMCAP Bus: 0 3.3.6.8 Device: 5 Offset: 6C Bit Attr Reset Value 31:27 RO 0h PME Support Bits 31, 30, and 27 must be set to 1 for PCI-PCI bridge structures representing ports on root complexes. 26 RO 0b D2 Support I/OxAPIC does not support power management state D2. 25 RO 0b D1 Support I/OxAPIC does not support power management state D1.
Processor Integrated I/O (IIO) Configuration Registers PMCSR Bus: 0 Offset: 70 Attr Reset Value 3 RO 1b No Soft Reset This bit indicates I/OxAPIC does not reset its registers when transitioning from D3hot to D0. 2 RV 0h Reserved 0h Power State This 2-bit field is used to determine the current power state of the function and to set a new power state as well.
Processor Integrated I/O (IIO) Configuration Registers 3.3.6.11 IOAPICTETPC—IOxAPIC Table Entry Target Programmable Control Register IOAPICTETPC Bus: 0 3.3.6.
Processor Integrated I/O (IIO) Configuration Registers 3.3.6.13 IOADSELS1—IOxAPIC DSELS Register 1 IOADSELS1 Bus: 0 Function: 4 Attr Reset Value 31:18 RV 0h Reserved 17:0 RWS 0h gttcfg2SIpcIOADels1[17:0] Bit 3.3.6.
Processor Integrated I/O (IIO) Configuration Registers 3.3.6.15 IOINTSRC1—IO Interrupt Source Register 1 IOINTSRC1 Bus: 0 Device: 5 Bit Attr Reset Value 31:21 RV 0h Function: 4 Offset: 2A4 Description Reserved Interrupt Source 1 20:0 3.3.6.
Processor Integrated I/O (IIO) Configuration Registers 3.3.6.17 IOREMGPECNT—Remote IO GPE Count Register IOREMGPECNT Bus: 0 3.3.6.
Processor Integrated I/O (IIO) Configuration Registers 3.3.7 I/OxAPIC Memory Mapped Registers I/OxAPIC has a direct memory mapped space. An index/data register pair is located within the directed memory mapped region and is used to access the redirection table entries. provides the direct memory mapped registers of the I/OxAPIC. The offsets shown in the table are from the base address in either ABAR or MBAR or both. Accesses to addresses beyond 40h return all 0s.
Processor Integrated I/O (IIO) Configuration Registers Table 3-20.
Processor Integrated I/O (IIO) Configuration Registers 3.3.7.1 INDX—Index Register The Index Register will select which indirect register appears in the window register to be manipulated by software. Software will program this register to select the desired APIC internal register. INDX Bus: 0 3.3.7.2 Device: 5 Offset: 0 Bit Attr Reset Value 7:0 RW-L 00h Bit 31:0 Description Index Indirect register to access. Note: Locked in D3hot state.
Processor Integrated I/O (IIO) Configuration Registers 3.3.7.4 EOI Register EOI Bus: 0 Bit 7:0 3.3.7.5 Device: 5 Offset: 40 Attr RW-L Function: 4 MMIO BAR: MBAR Reset Value Description 00h EOI The EOI register is present to provide a mechanism to efficiently convert level interrupts to edge triggered MSI interrupts.
Processor Integrated I/O (IIO) Configuration Registers 3.3.7.7 ARBID—Arbitration ID Register This is a legacy register carried over from days of serial bus interrupt delivery. This register has no meaning in IIO. It just tracks the APICID register for compatibility reasons. ARBID Bus: 0 3.3.7.8 Device: 5 Offset: 2 Bit Attr Reset Value 27:24 RO 0b Arbitration ID Just tracks the APICID register.
Processor Integrated I/O (IIO) Configuration Registers 3.3.7.9 RTL[0:23]—Redirection Table Low DWord Register The information in this register along with Redirection Table High DWord register is used to construct the MSI interrupt. There is one of these pairs of registers for every interrupt. The first interrupt has the redirection registers at offset 10h. The second interrupt at 12h, third at 14h, etc. until the final interrupt (interrupt 23) at 3Eh.
Processor Integrated I/O (IIO) Configuration Registers RTL[0:23] Bus: 0 Bit 3.3.7.10 Attr Function: 4 MMIO BAR: WINDOW_0 Reset Value Description 12 RO 0b Delivery Status When trigger mode is set to level and the entry is unmasked, this bit indicates the state of the level interrupt. That is, 1b if interrupt is asserted; else 0b. When the trigger mode is set to level but the entry is masked, this bit is always 0b. This bit is always 0b when trigger mode is set to edge.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8 Intel® VT-d Memory Mapped Register Intel VT-d registers are all addressed using aligned DWord or aligned QWord accesses. Any combination of bits is allowed within a DWord or QWord access. The Intel VT-d remap engine registers corresponding to the non-Isochronous port represented by Device 0, occupy the first 4 K of offset starting from the base address defined by VTBAR register.
Processor Integrated I/O (IIO) Configuration Registers Table 3-21.
Processor Integrated I/O (IIO) Configuration Registers Table 3-22.
Processor Integrated I/O (IIO) Configuration Registers Table 3-23.
Processor Integrated I/O (IIO) Configuration Registers Table 3-24.
Processor Integrated I/O (IIO) Configuration Registers Table 3-25.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.1 VTD0_VERSION—Version Number Register VTD0_VERSION Bus: 0 Bit 3.3.8.
Processor Integrated I/O (IIO) Configuration Registers VTD0_CAP Bus: 0 Bit 3.3.8.3 Attr Function: 0 Reset Value MMIO BAR: VTBAR Description 7 RO 0b CM The processor does not cache invalid pages. This bit should always be set to 0 on hardware. It can be set to 1 when doing software virtualization of Intel VT-d. 6 RO 1b PHMR Support The processor supports protected high memory range. 5 RO 1b PLMR Support The processor supports protected low memory range.
Processor Integrated I/O (IIO) Configuration Registers VTD0_EXT_CAP Bus: 0 Function: 0 MMIO BAR: VTBAR Bit Attr Reset Value 1 RWO 1b Queued Invalidation Support IIO supports this 0b Coherency Support BIOS can write to this bit to indicate to hardware to either snoop or not-snoop the DMA/Interrupt table structures in memory (root/context/pd/pt/irt).
Processor Integrated I/O (IIO) Configuration Registers VTD0_GLBCMD Bus: 0 Function: 0 MMIO BAR: VTBAR Bit Attr Reset Value 27 RO 0b Write Buffer Flush Not Applicable to the processor 0b Queued Invalidation Enable Software writes to this field to enable queued invalidations. 0 = Disable queued invalidations. In this case, invalidations must be performed through the Context Command and IOTLB Invalidation Unit registers. 1 = Enable use of queued invalidations.
Processor Integrated I/O (IIO) Configuration Registers VTD0_GLBCMD Bus: 0 Bit 3.3.8.5 Attr Device: 5 Offset: 18h Function: 0 MMIO BAR: VTBAR Reset Value Description 23 RW 0b Compatibility Format Interrupt Software writes to this field to enable or disable Compatibility Format interrupts on Intel 64 platforms. The value in this field is effective only when interruptremapping is enabled and Legacy Interrupt Mode is active. 0 = Block Compatibility format interrupts.
Processor Integrated I/O (IIO) Configuration Registers VTD0_GLBSTS Bus: 0 3.3.8.6 Device: 5 Offset: 1Ch Bit Attr Reset Value 22:0 RV 0h Reserved VTD0_ROOTENTRYADD—Root Entry Table Address Register Bit Attr Function: 0 MMIO BAR: VTBAR Reset Value Description 63:12 RW 0h Root Entry Table Base Address 4K aligned base address for the root entry table. The processor does not use bits 63:43 and checks for them to be 0.
Processor Integrated I/O (IIO) Configuration Registers VTD0_CTXCMD Bus: 0 Bit 62:61 Attr RW Device: 5 Offset: 28h Function: 0 MMIO BAR: VTBAR Reset Value Description 0b Context Invalidation Request Granularity When requesting hardware to invalidate the context-entry cache (by setting the ICC field), software writes the requested invalidation granularity through this field. Following are the encodings for the 2-bit IRG field. 00 = Reserved.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.8 VTD0_FLTSTS—Fault Status Register VTD0_FLTSTS Bus: 0 246 Device: 5 Offset: 34h Bit Attr Reset Value 31:16 RV 0h Reserved Function: 0 MMIO BAR: VTBAR Description 15:8 ROS-V 0h Fault Record Index This field is valid only when the Primary Fault Pending field is set.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.9 VTD0_FLTEVTCTRL—Fault Event Control Register VTD0_FLTEVTCTRL Bus: 0 Device: 5 Offset: 38h Bit 31 3.3.8.10 Attr RW Function: 0 MMIO BAR: VTBAR Reset Value Description 1b Interrupt Message Mask 1 = Hardware is prohibited from issuing interrupt message requests. 0 = Software has cleared this bit to indicate interrupt service is available.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.11 VTD0_FLTEVTADDR—Fault Event Address Register VTD0_FLTEVTADDR Bus: 0 Device: 5 Offset: 40h 3.3.8.12 Bit Attr Reset Value 63:2 RW 000000 000000 0000h 1:0 RV 0h Bit Description Interrupt Address The interrupt address is interpreted as the address of any other interrupt from a PCI Express port.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.14 VTD0_PROT_LOW_MEM_LIMIT—Protected Memory Low Limit Register VTD0_PROT_LOW_MEM_LIMIT Bus: 0 Device: 5 Offset: 6Ch Bit 3.3.8.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.17 VTD0_INV_QUEUE_HEAD—Invalidation Queue Header Pointer Register VTD0_INV_QUEUE_HEAD Bus: 0 Device: 5 Offset: 80h 3.3.8.18 Bit Attr Reset Value 63:19 RV 0h 18:4 RO-V 0000h 3:0 RV 0h Reserved Queue Head This field specifies the offset (128-bit aligned) to the invalidation queue for the command that will be fetched next by hardware.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.20 VTD0_INV_COMP_STATUS—Invalidation Completion Status Register VTD0_INV_COMP_STATUS Bus: 0 Device: 5 Offset: 9Ch 3.3.8.21 Function: 0 MMIO BAR: VTBAR Bit Attr Reset Value 31:1 RV 0h Reserved 0 RW1CS 0b Invalidation Wait Descriptor Complete This field indicates completion of Invalidation Wait Descriptor with Interrupt Flag (IF) field set.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.22 VTD0_INV_COMP_EVT_DATA—Invalidation Completion Event Data Register VTD0_INV_COMP_EVT_DATA Bus: 0 Device: 5 Offset: A4h Bit 3.3.8.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.25 VTD0_FLTREC0_GPA—Fault Record Register VTD0_FLTREC0_GPA Bus: 0 Device: 5 Offset: 100h 3.3.8.26 MMIO BAR: VTBAR Bit Attr Reset Value 63:12 ROS-V 0h GPA 4k aligned GPA for the faulting transaction. Valid only when F field is set 11:0 RV 0h Reserved Description VTD0_FLTREC0_SRC—Fault Record Register VTD0_FLTREC0_SRC Bus: 0 Device: 5 Offset: 108h Bit 63 3.3.8.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.28 VTD0_FLTREC1_SRC—Fault Record Register VTD0_FLTREC1_SRC Bus: 0 Device: 5 Offset: 118h Bit 63 3.3.8.29 Attr RW1CS MMIO BAR: VTBAR Reset Value Description 0b Fault Hardware sets this field to indicate a fault is logged in this fault recording register. The F field is set by hardware after the details of the fault is recorded in the PADDR, SID, FR and T fields.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.30 VTD0_FLTREC2_SRC—Fault Record Register VTD0_FLTREC2_SRC Bus: 0 Device: 5 Offset: 128h Bit 63 3.3.8.31 Attr RW1CS Function: 0 MMIO BAR: VTBAR Reset Value Description 0b Fault Hardware sets this field to indicate a fault is logged in this fault recording register. The F field is set by hardware after the details of the fault is recorded in the PADDR, SID, FR and T fields.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.32 VTD0_FLTREC3_SRC—Fault Record Register VTD0_FLTREC3_SRC Bus: 0 Device: 5 Offset: 138h Bit 63 3.3.8.33 Attr RW1CS MMIO BAR: VTBAR Reset Value Description 0b Fault Hardware sets this field to indicate a fault is logged in this fault recording register. The F field is set by hardware after the details of the fault is recorded in the PADDR, SID, FR and T fields.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.34 VTD0_FLTREC4_SRC—Fault Record Register VTD0_FLTREC4_SRC Bus: 0 Device: 5 Offset: 148h Bit 63 3.3.8.35 Attr RW1CS Function: 0 MMIO BAR: VTBAR Reset Value Description 0b Fault Hardware sets this field to indicate a fault is logged in this fault recording register. The F field is set by hardware after the details of the fault is recorded in the PADDR, SID, FR and T fields.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.36 VTD0_FLTREC5_SRC—Fault Record Register VTD0_FLTREC5_SRC Bus: 0 Device: 5 Offset: 158h Bit 63 3.3.8.37 Attr RW1CS MMIO BAR: VTBAR Reset Value Description 0b Fault Hardware sets this field to indicate a fault is logged in this fault recording register. The F field is set by hardware after the details of the fault is recorded in the PADDR, SID, FR and T fields.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.38 VTD0_FLTREC6_SRC—Fault Record Register VTD0_FLTREC6_SRC Bus: 0 Device: 5 Offset: 168h Bit 63 3.3.8.39 Attr RW1CS Function: 0 MMIO BAR: VTBAR Reset Value Description 0b Fault Hardware sets this field to indicate a fault is logged in this fault recording register. The F field is set by hardware after the details of the fault is recorded in the PADDR, SID, FR and T fields.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.40 VTD0_FLTREC7_SRC—Fault Record Register VTD0_FLTREC7_SRC Bus: 0 Device: 5 Offset: 178h Bit 63 3.3.8.41 Attr RW1CS MMIO BAR: VTBAR Reset Value Description 0b Fault Hardware sets this field to indicate a fault is logged in this fault recording register. The F field is set by hardware after the details of the fault is recorded in the PADDR, SID, FR and T fields.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.42 VTD0_IOTLBINV—IOTLB Invalidate Register VTD0_IOTLBINV Bus: 0 Device: 5 Offset: 208h Bit Attr Function: 0 MMIO BAR: VTBAR Reset Value Description 63 RW 0b Invalidate IOTLB cache Software requests IOTLB invalidation by setting this field. Software must also set the requested invalidation granularity by programming the IIRG field. Hardware clears the IVT field to indicate the invalidation request is complete.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.43 VTD1_VERSION—Version Number Register VTD1_VERSION Bus: 0 Bit 3.3.8.
Processor Integrated I/O (IIO) Configuration Registers VTD1_CAP Bus: 0 3.3.8.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.46 VTD1_GLBCMD—Global Command Register VTD1_GLBCMD Bus: 0 Bit 31 RW Function: 0 MMIO BAR: VTBAR Reset Value Description 0b Translation Enable Software writes to this field to request hardware to enable/disable DMAremapping hardware. 0 = Disable DMA-remapping hardware 1 = Enable DMA-remapping hardware Hardware reports the status of the translation enable operation through the TES field in the Global Status register.
Processor Integrated I/O (IIO) Configuration Registers VTD1_GLBCMD Bus: 0 Bit 25 24 Attr RW RW Device: 5 Offset: 1018h Function: 0 MMIO BAR: VTBAR Reset Value Description 0b Interrupt Remapping Enable 0 = Disable Interrupt Remapping Hardware 1 = Enable Interrupt Remapping Hardware Hardware reports the status of the interrupt-remap enable operation through the IRES field in the Global Status register.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.47 VTD1_GLBSTS—Global Status Register VTD1_GLBSTS Bus: 0 MMIO BAR: VTBAR Attr Reset Value Description 31 RO 0b Translation Enable Status When set, indicates that translation hardware is enabled and when clear indicates the translation hardware is not enabled. 30 RO 0b Set Root Table Pointer Status This field indicates the status of the root- table pointer in hardware.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.49 VTD1_CTXCMD—Context Command Register VTD1_CTXCMD Bus: 0 Bit 63 62:61 Attr RW RW Device: 5 Offset: 1028 Function: 0 MMIO BAR: VTBAR Reset Value Description 0b Invalidate Context Entry Cache Software requests invalidation of context-cache by setting this field. Software must also set the requested invalidation granularity by programming the CIRG field.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.50 VTD1_FLTSTS—Fault Status Register VTD1_FLTSTS Bus: 0 268 Device: 5 Offset: 1034h Bit Attr Reset Value 31:16 RV 0h Reserved Function: 0 MMIO BAR: VTBAR Description 15:8 ROS-V 0h Fault Record Index This field is valid only when the Primary Fault Pending field is set.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.51 VTD1_FLTEVTCTRL—Fault Event Control Register VTD1_FLTEVTCTRL Bus: 0 Device: 5 Offset: 1038h Bit 31 3.3.8.52 Attr RW Function: 0 MMIO BAR: VTBAR Reset Value Description 1b Interrupt Message Mask 0 = Hardware is prohibited from issuing interrupt message requests. 1 = Software has cleared this bit to indicate interrupt service is available.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.53 VTD1_FLTEVTADDR—Fault Event Address Register VTD1_FLTEVTADDR Bus: 0 Device: 5 Offset: 1040h 3.3.8.54 Bit Attr Reset Value 63:2 RW 000000 000000 0000h 1:0 RV 0h Bit Description Interrupt Address The interrupt address is interpreted as the address of any other interrupt from a PCI Express port.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.56 VTD1_PROT_LOW_MEM_LIMIT—Protected Memory Low Limit Register VTD1_PROT_LOW_MEM_LIMIT Bus: 0 Device: 5 Offset: 106Ch Bit 3.3.8.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.59 VTD1_INV_QUEUE_HEAD—Invalidation Queue Header Pointer Register VTD1_INV_QUEUE_HEAD Bus: 0 Device: 5 Offset: 1080h 3.3.8.60 Bit Attr Reset Value 63:19 RV 0h 18:4 RO-V 0000h 3:0 RV 0h Reserved Queue Head This field specifies the offset (128-bit aligned) to the invalidation queue for the command that will be fetched next by hardware.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.62 VTD1_INV_COMP_STATUS—Invalidation Completion Status Register VTD1_INV_COMP_STATUS Bus: 0 Device: 5 Offset: 109Ch 3.3.8.63 MMIO BAR: VTBAR Bit Attr Reset Value 31:1 RV 0h Reserved 0 RW1CS 0b Invalidation Wait Descriptor Complete This field indicates completion of Invalidation Wait Descriptor with Interrupt Flag (IF) field set.
Processor Integrated I/O (IIO) Configuration Registers VTD1_INV_COMP_EVT_DATA Bus: 0 Device: 5 Offset: 10A4h 3.3.8.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.68 VTD1_FLTREC0_SRC—Fault Record Register VTD1_FLTREC0_SRC Bus: 0 Device: 5 Offset: 1108h Bit 63 3.3.8.69 Attr RW1CS Function: 0 MMIO BAR: VTBAR Reset Value Description 0b Fault Hardware sets this field to indicate a fault is logged in this fault recording register. The F field is set by hardware after the details of the fault is recorded in the PADDR, SID, FR and T fields.
Processor Integrated I/O (IIO) Configuration Registers 3.3.8.70 VTD1_IOTLBINV—IOTLB Invalidate Register VTD1_IOTLBINV Bus: 0 Device: 5 Offset: 1208 Bit Attr Function: 0 MMIO BAR: VTBAR Reset Value Description 63 RW 0b Invalidate IOTLB cache Software requests IOTLB invalidation by setting this field. Software must also set the requested invalidation granularity by programming the IIRG field.Hardware clears the IVT field to indicate the invalidation request is complete.
Processor Uncore Configuration Registers 4 Processor Uncore Configuration Registers This chapter also contains the Integrated Memory Controller Registers for all 4 Channels and the Power Control Unit (PCU) registers. 4.1 PCI Standard Registers These registers appear in every function for every uncore device and can be accessed using the provided offset. 4.1.1 VID—Vendor Identification Register VID Offset: 0h 4.1.
Processor Uncore Configuration Registers 4.1.3 PCICMD—PCI Command Register PCICMD Offset: 4h 278 Bit Attr Reset Value 15:11 RV 0h Reserved 10 RO 0b INTx Disable Not applicable for these devices 9 RO 0b Fast Back-to-Back Enable Not applicable to PCI Express and is hardwired to 0 8 RO 0b SERR Enable This bit has no impact on error reporting from these devices 7 RO 0b IDSEL Stepping/Wait Cycle Control Not applicable to internal devices. Hardwired to 0.
Processor Uncore Configuration Registers 4.1.4 PCISTS—PCI Status Register PCISTS Offset: 6h Bit Attr Reset Value Description 15 RO 0b Detected Parity Error This bit is set when the device receives a packet on the primary side with an uncorrectable data error (including a packet with poison bit set) or an uncorrectable address/control parity error. The setting of this bit is regardless of the Parity Error Response bit (PERRE) in the PCICMD register. R2PCIe will never set this bit.
Processor Uncore Configuration Registers 4.1.5 RID—Revision Identification Register RID Offset: 8h Bit 7:0 4.1.6 Attr RO Reset Value Description 00h Revision_ID Reflects the Uncore Revision ID after reset. Reflects the Compatibility Revision ID after BIOS writes 69h to any RID register in any processor function. Implementation Note: Read and write requests from the host to any RID register in any processor function are re-directed to the IIO cluster.
Processor Uncore Configuration Registers 4.1.9 HDR—Header Type Register HDR Offset: Eh 4.1.10 Bit Attr Reset Value 7 RO 1b 6:0 RO 00h Description Multi-function Device This bit defaults to 1b since all these devices are multi-function Configuration Layout This field identifies the format of the configuration header layout. It is Type 0 for all these devices. The default is 00h, indicating a ’endpoint device’. BIST—Built-In Self Test Register BIST Offset: Fh 4.1.
Processor Uncore Configuration Registers 4.1.13 CAPPTR—Capability Pointer Register CAPPTR Offset: 34h 4.1.14 Bit Attr Reset Value 7:0 RO 00h Description Capability Pointer Points to the first capability structure for the device which is the PCIe capability. INTL—Interrupt Line Register INTL Offset: 3Ch 4.1.15 Bit Attr Reset Value 7:0 RO 00h Description Interrupt Line Not applicable for these devices INTPIN—Interrupt Pin Register INTPIN Offset: 3Dh 4.1.
Processor Uncore Configuration Registers 4.2 Integrated Memory Controller Configuration Registers The Integrated Memory Controller unit contains four controllers. Up to four channels can be operated independently. The DRAM controllers share a common address decode. Configuration registers may be per channel or common. 4.2.1 Processor Registers All Integrated Memory Controller registers listed below are specific to the the processor. 4.2.
Processor Uncore Configuration Registers Table 4-2.
Processor Uncore Configuration Registers Table 4-3.
Processor Uncore Configuration Registers Table 4-4.
Processor Uncore Configuration Registers Table 4-5.
Processor Uncore Configuration Registers Table 4-6.
Processor Uncore Configuration Registers Table 4-7.
Processor Uncore Configuration Registers Table 4-8.
Processor Uncore Configuration Registers Table 4-9.
Processor Uncore Configuration Registers Table 4-10.
Processor Uncore Configuration Registers Table 4-11.
Processor Uncore Configuration Registers . Table 4-12.
Processor Uncore Configuration Registers Table 4-13.
Processor Uncore Configuration Registers Table 4-14.
Processor Uncore Configuration Registers Table 4-15.
Processor Uncore Configuration Registers Table 4-16.
Processor Uncore Configuration Registers Table 4-17.
Processor Uncore Configuration Registers Table 4-18.
Processor Uncore Configuration Registers 4.2.3 CBO unicast CSRs 4.2.3.1 RTID_Config_Pool01_Size—Ring Global Configuration Register This control register contain the RTID pool information for Cbo RTID_Config_Pool01_Size Bus: 1 Device: 12 Offset: 40h Bus: 1 Device: 12 Bus: 1 Device: 12 Bus: 1 Device: 12 Bus: 1 Device: 12 Bus: 1 Device: 13 Bus: 1 Device: 13 Bus: 1 Device: 13 Bus: 1 Device: 13 4.2.3.
Processor Uncore Configuration Registers 4.2.3.3 RTID_Config_Pool45_Size—Ring Global Configuration Register This control register contain the RTID pool information for Cbo. RTID_Config_Pool45_Size Bus: 1 Device: 12 Offset: 48h Bus: 1 Device: 12 Bus: 1 Device: 12 Bus: 1 Device: 12 Bus: 1 Device: 12 Bus: 1 Device: 13 Bus: 1 Device: 13 Bus: 1 Device: 13 Bus: 1 Device: 13 4.2.3.
Processor Uncore Configuration Registers 4.2.3.5 VNA_Credit_Config—VNA Credit Configuration Register Register related to VNA Credit Configuration VNA_Credit_Config Bus: 1 Device: 12 Offset: 54h Bus: 1 Device: 12 Bus: 1 Device: 12 Bus: 1 Device: 12 Bus: 1 Device: 12 Bus: 1 Device: 13 Bus: 1 Device: 13 Bus: 1 Device: 13 Bus: 1 Device: 13 4.2.3.
Processor Uncore Configuration Registers 4.2.3.
Processor Uncore Configuration Registers 4.2.3.10 CBO_GDXC_PKT_CNTRL—CBO GDXC Packet Control Register This register is controlled by lock bit GDXCLCK in XXX register. The register may be readable with the lock bit set but no writes will take effect unless the lock bit is set to 0.
Processor Uncore Configuration Registers 4.2.3.11 RTID_Config_Pool01_Base—Ring Global Configuration Register This control register contain the RTID pool information for Cbo.
Processor Uncore Configuration Registers 4.2.3.12 RTID_Config_Pool23_Base—Ring Global Configuration Register This control register contain the RTID pool information for Cbo.
Processor Uncore Configuration Registers 4.2.3.13 RTID_Config_Pool45_Base—Ring Global Configuration Register This control register contain the RTID pool information for Cbo.
Processor Uncore Configuration Registers 4.2.3.14 RTID_Config_Pool67_Base—Ring Global Configuration Register This control register contain the RTID pool information for Cbo.
Processor Uncore Configuration Registers 4.2.3.15 RTID_Pool_Config—Ring Global Configuration Register This control register contain the RTID pool information for Cbo.
Processor Uncore Configuration Registers 4.2.3.16 RTID_Config_Pool01_Base_Shadow—Ring Global Configuration Shadow Register This control register contain the RTID pool information for Cbo.
Processor Uncore Configuration Registers 4.2.3.17 RTID_Config_Pool23_Base_Shadow—Ring Global Configuration Shadow Register This control register contain the RTID pool information for Cbo.
Processor Uncore Configuration Registers 4.2.3.18 RTID_Config_Pool45_Base_Shadow—Ring Global Configuration Shadow Register This control register contain the RTID pool information for Cbo.
Processor Uncore Configuration Registers 4.2.3.19 RTID_Config_Pool67_Base_Shadow—Ring Global Configuration Shadow Register This control register contain the RTID pool information for Cbo.
Processor Uncore Configuration Registers 4.2.3.20 RTID_Pool_Config_Shadow— Ring Global Configuration Shadow Register This control register contain the RTID pool information for Cbo.
Processor Uncore Configuration Registers 4.2.4 System Address Decoder Registers (CBO) 4.2.4.1 PAM0123—CBO SAD PAM Register PAM0123 Bus: 1 316 Device: 12 Bit Attr Reset Value 31:30 RV 0h Reserved Function: 6 Offset: 40h Description 29:28 RW 0h PAM3_HIENABLE: 0D4000h–0D7FFFh Attribute (HIENABLE) This field controls the steering of read and write cycles that address the BIOS area from 0D4000h to 0D7FFFh. 00 = DRAM Disabled: All accesses are directed to DMI.
Processor Uncore Configuration Registers PAM0123 Bus: 1 Bit 4.2.4.2 Attr Device: 12 Function: 6 Offset: 40h Reset Value Description 9:8 RW 0h PAM1_LOENABLE: 0C0000h-0C3FFFh Attribute (LOENABLE) This field controls the steering of read and write cycles that address the BIOS area from 0C0000h to 0C3FFFh. 00 = DRAM Disabled: All accesses are directed to DMI. 01 = Read Only: All reads are sent to DRAM. All writes are forwarded to DMI. 10 = Write Only: All writes are send to DRAM.
Processor Uncore Configuration Registers PAM456 Bus: 1 Bit Attr Function: 6 Offset: 44h Reset Value Description 9:8 RW 0h PAM5_LOENABLE: 0E0000h-0E3FFFh Attribute (LOENABLE) This field controls the steering of read and write cycles that address the BIOS area from 0E0000h to 0E3FFFh. 00 = DRAM Disabled: All accesses are directed to DMI. 01 = Read Only: All reads are sent to DRAM. All writes are forwarded to DMI. 10 = Write Only: All writes are send to DRAM. Reads are serviced by DMI.
Processor Uncore Configuration Registers 4.2.4.3 SMRAMC—System Management RAM Control Register SMRAMC Bus: 1 Device: 12 Function: 6 Offset: 4Ch Bit Attr Reset Value 31:7 RV 0h Reserved 0b D_OPEN: SMM Space Open (D_OPEN) When D_OPEN=1 and D_LCK=0, the SMM space DRAM is made visible even when SMM decode is not active. This is intended to help BIOS initialize SMM space. Software should ensure that D_OPEN=1 and D_CLS=1 are note set at the same time.
Processor Uncore Configuration Registers 4.2.4.4 MESEG_BASE—Manageability Engine Base Address Register MESEG_BASE Bus: 1 4.2.4.5 Bit Attr Reset Value 63:46 RV 0h 45:19 RW-LB 000000 0h 18:0 RV 0h Function: 6 Offset: 70h Description Reserved MEBASE This field corresponds to A[45:19] of the base address memory range that is allocated to the ME.
Processor Uncore Configuration Registers 4.2.4.6 DRAM_RULE[0:9]—DRAM Rule 0 Register DRAM_RULE[0:9] Bus: 1 Device: 12 Bit Attr Reset Value 31:26 RV 0h 25:6 RW-LB 00000h 5:4 RV 0h 3:2 4.2.4.7 RW-LB 00b Function: 6 Offset: 80h Description Reserved Limit This field correspond to Addr[45:26] of the DRAM rule top limit address. Must be strictly greater then previous rule, even if this rule is disabled, unless this rule and all following rules are disabled.
Processor Uncore Configuration Registers 4.2.4.8 DRAM_RULE_1—DRAM Rule 1 Register DRAM_RULE_1 Bus: 1 Bit Attr Reset Value 31:26 RV 0h 25:6 RW-LB 00000h 5:4 RV 0h 3:2 4.2.4.9 Device: 12 RW-LB 00b Offset: 88h Description Reserved Limit This field correspond to Addr[45:26] of the DRAM rule top limit address. Must be strictly greater then previous rule, even if this rule is disabled, unless this rule and all following rules are disabled.
Processor Uncore Configuration Registers 4.2.4.10 DRAM_RULE_2—DRAM Rule 2 Register DRAM_RULE_2 Bus: 1 Bit Attr Reset Value 31:26 RV 0h 25:6 RW-LB 00000h 5:4 RV 0h 3:2 4.2.4.11 Device: 12 RW-LB 00b Function: 6 Offset: 90h Description Reserved Limit This correspond to Addr[45:26] of the DRAM rule top limit address. Must be strictly greater then previous rule, even if this rule is disabled, unless this rule and all following rules are disabled.
Processor Uncore Configuration Registers 4.2.4.12 DRAM_RULE_3—DRAM Rule 3 Register DRAM_RULE_3 Bus: 1 4.2.4.13 Device: 12 Bit Attr Reset Value 31:26 RV 0h 25:6 RW-LB 00000h 5:4 RV 0h 3:2 RW-LB 00b Offset: 98h Description Reserved Limit This field correspond to Addr[45:26] of the DRAM rule top limit address. Must be strictly greater then previous rule, even if this rule is disabled, unless this rule and all following rules are disabled.
Processor Uncore Configuration Registers 4.2.4.14 DRAM_RULE_4—DRAM Rule 4 Register DRAM_RULE_4 Bus: 1 Bit Attr Reset Value 31:26 RV 0h 25:6 RW-LB 00000h 5:4 RV 0h 3:2 4.2.4.15 Device: 12 RW-LB 00b Function: 6 Offset: A0h Description Reserved Limit This field correspond to Addr[45:26] of the DRAM rule top limit address. Must be strictly greater then previous rule, even if this rule is disabled, unless this rule and all following rules are disabled.
Processor Uncore Configuration Registers 4.2.4.16 DRAM_RULE_5—DRAM Rule 5 Register DRAM_RULE_5 Bus: 1 Bit Attr Reset Value 31:26 RV 0h 25:6 RW-LB 00000h 5:4 RV 0h 3:2 4.2.4.17 Device: 12 RW-LB 00b Offset: A8h Description Reserved Limit This field correspond to Addr[45:26] of the DRAM rule top limit address. Must be strictly greater then previous rule, even if this rule is disabled, unless this rule and all following rules are disabled.
Processor Uncore Configuration Registers 4.2.4.18 DRAM_RULE_6—DRAM Rule 6 Register DRAM_RULE_6 Bus: 1 Bit Attr Reset Value 31:26 RV 0h 25:6 RW-LB 00000h 5:4 RV 0h 3:2 4.2.4.19 Device: 12 RW-LB 00b Function: 6 Offset: B0h Description Reserved Limit This correspond to Addr[45:26] of the DRAM rule top limit address. Must be strictly greater then previous rule, even if this rule is disabled, unless this rule and all following rules are disabled.
Processor Uncore Configuration Registers 4.2.4.20 DRAM_RULE_7—DRAM Rule 7 Register DRAM_RULE_7 Bus: 1 Bit Attr Reset Value 31:26 RV 0h 25:6 RW-LB 00000h 5:4 RV 0h 3:2 4.2.4.21 Device: 12 RW-LB 00b Offset: B8h Description Reserved Limit This field correspond to Addr[45:26] of the DRAM rule top limit address. Must be strictly greater then previous rule, even if this rule is disabled, unless this rule and all following rules are disabled.
Processor Uncore Configuration Registers 4.2.4.22 DRAM_RULE_8—DRAM Rule 8 Register DRAM_RULE_8 Bus: 1 Bit Attr Reset Value 31:26 RV 0h 25:6 RW-LB 00000h 5:4 RV 0h 3:2 4.2.4.23 Device: 12 RW-LB 00b Function: 6 Offset: C0h Description Reserved Limit This field correspond to Addr[45:26] of the DRAM rule top limit address. Must be strictly greater then previous rule, even if this rule is disabled, unless this rule and all following rules are disabled.
Processor Uncore Configuration Registers 4.2.4.24 DRAM_RULE_9—DRAM Rule 9 Register DRAM_RULE_9 Bus: 1 Bit Attr Reset Value 31:26 RV 0h 25:6 RW-LB 00000h 5:4 RV 0h 3:2 4.2.4.25 Device: 12 RW-LB 00b Offset: C8h Description Reserved Limit This field correspond to Addr[45:26] of the DRAM rule top limit address. Must be strictly greater then previous rule, even if this rule is disabled, unless this rule and all following rules are disabled.
Processor Uncore Configuration Registers 4.2.5 Caching Agent Broadcast Registers (CBo) 4.2.5.1 Cbo_ISOC_Config—Cbo Isochrony Configuration Register Cbo_ISOC_Config Bus: 1 Device: 12 4.2.5.2 Function: 7 Offset: 44h Bit Attr Reset Value 31:1 RV 0h Reserved 0 RW 0h Isoc_Enable Enable ISOC mode. This will be used for TOR pipeline to reserve TOR entries for ISOC.
Processor Uncore Configuration Registers Cbo_Coh_Config Bus: 1 4.2.5.
Processor Uncore Configuration Registers MMIO_RULE[0:7] Bus: N Device: 13 Function: 6 Offset: 80h, 88h, 90h, 98h, A0h, A8h, B0h, B8h Bit Attr Reset Value Description 45:26 RW-LB 00000h Limit address This field correspond to Addr[45:26] of the MMIO rule top limit address. Both base and limit must match to declare a match to this MMIO rule.
Processor Uncore Configuration Registers 4.2.5.6 MMCFG_Rule—MMCFG Rule for Interleave Decoder Register MMCFG_Rule Bus: N 4.2.5.7 Device: 13 Bit Attr Reset Value 63:46 RV 0h 45:20 RW-LB 000000 0h 19:3 RV 0h 2:1 RW-LB 00b 0 RW-LB 0h Offset: C0h Description Reserved Base address This field correspond to Addr[45:20] of the MMCFG rule base address. The granularity of MMCFG rule is 64 MB.
Processor Uncore Configuration Registers 4.2.5.8 MMCFG_Target_LIST—MMCFG Target List Register MMCFG_Target_LIST Bus: N Device: 13 4.2.5.9 Function: 6 Bit Attr Reset Value 31:24 RV 0h Reserved 23:21 RW-LB 0h Package7 NodeID of the MMCFG target. 20:18 RW-LB 0h Package6 NodeID of the MMCFG target. 17:15 RW-LB 0h Package5 NodeID of the MMCFG target. 14:12 RW-LB 0h Package4 NodeID of the MMCFG target. 11:9 RW-LB 0h Package3 NodeID of the MMCFG target.
Processor Uncore Configuration Registers 4.2.5.10 IOAPIC_Target_LIST—IOAPIC Target List Register IOAPIC_Target_LIST Bus: N Device: 13 4.2.5.11 Bit Attr Reset Value 31:24 RV 0h Reserved 23:21 RW-LB 0h Package7 NodeID of the IOAPIC target. 20:18 RW-LB 0h Package6 NodeID of the IOAPIC target. 17:15 RW-LB 0h Package5 NodeID of the IOAPIC target. 14:12 RW-LB 0h Package4 NodeID of the IOAPIC target. 11:9 RW-LB 0h Package3 NodeID of the IOAPIC target.
Processor Uncore Configuration Registers 4.2.5.12 SAD_Control—SAD Control Register SAD_Control Bus: N 4.2.6 Device: 13 Function: 6 Bit Attr Reset Value 31:3 RV 0h Reserved 2:0 RW-L 0h Local_NodeID NodeID of the local Socket. Offset: F4h Description Integrated Memory Controller Target Address Registers This section describes the PCI/PCIe registers that are present in this unit.
Processor Uncore Configuration Registers 4.2.6.2 MCMTR—MC Memory Technology Register MCMTR Bus: 1 338 Device: 15 Function: 0 Offset: 7Ch Bit Attr Reset Value 31:10 RV 0h Reserved 8 RW-LB 0b NORMAL 0 = IOSAV mode 1 = Normal Mode 7:4 RV 0h Reserved 3 RW-LB 0b DIR_EN Note: This bit will only work if the SKU is enabled for this feature. Changing this bit will require BIOS to re-initialize the memory.
Processor Uncore Configuration Registers 4.2.6.3 TADWAYNESS_[0:11]—TAD Range Wayness, Limit and Target Register There are total of 12 TAD ranges (N+P+1= number of TAD ranges; P= how many times channel interleave changes within the SAD ranges.). TADWAYNESS_[0:11] Bus: 1 Device: 15 Function: 0 Bus: 1 Function: 0 Bit Attr Reset Value Description 31:12 RW-LB 00000h TAD_LIMIT highest address of the range in system address space, 64 MB granularity; that is, TADRANGLIMIT[45:26]. 11:10 9:8 4.2.
Processor Uncore Configuration Registers 4.2.6.5 MC_INIT_STATE_G—Initialization State for Boot, Training and IOSAV Register This register defines the high-level behavior in IOSAV mode.
Processor Uncore Configuration Registers 4.2.6.6 RCOMP_TIMER—RCOMP Wait Timer Register Defines the time from IO starting to run RCOMP evaluation until RCOMP results are definitely ready.
Processor Uncore Configuration Registers 4.2.7 Integrated Memory Controller MemHot Registers These registers Control for the Integrated Memory Controller thermal throttle logic for each channel. 4.2.7.1 MH_MAINCNTL—MEMHOT Main Control Register MH_MAINCNTL Bus: 1 Function: 0 Offset: 104h Bit Attr Reset Value 31:19 RV 0h Reserved 18 RW 0h MHOT_EXT_SMI_EN Generate SMI event when either MEMHOT[1:0]# is externally asserted.
Processor Uncore Configuration Registers 4.2.7.2 MH_SENSE_500NS_CFG—MEMHOT Sense and 500 ns Config Register MH_SENSE_500NS_CFG Bus: 1 Device: 15 Bit Attr Reset Value 31:26 RV 0h 25:16 RW 0C8h Offset: 10Ch Description Reserved MH_SENSE_PERIOD MEMHOT Input Sense Period in number of CNTR_500_NANOSEC. BIOS calculates the number of CNTR_500_NANOSEC for 50 usec/100 usec/200 usec/400 usec. 15:13 RW 2h MH_IN_SENSE_ASSERT MEMHOT Input Sense Assertion Time in number of CNTR_500_NANOSEC.
Processor Uncore Configuration Registers 4.2.7.4 MH_IO_500NS_CNTR—MEMHOT Input Output and 500ns Counter Register MH_IO_500NS_CNTR Bus: 1 Device: 15 Bit 31:22 RW-LV Description 000h MH1_IO_CNTR MEM_HOT[1:0]# Input Output Counter in number of CNTR_500_NANOSEC. When MH0_IO_CNTR is zero, the counter is loaded with MH_SENSE_PERIOD in the next CNTR_500_NANOSEC. When count is greater than MH_IN_SENSE_ASSERT, the MEM_HOT[1]# output driver may be turned on if the corresponding MEM_HOT#event is asserted.
Processor Uncore Configuration Registers 4.2.7.5 MH_CHN_ASTN—MEMHOT Domain Channel Association Register MH_CHN_ASTN Bus: 1 Device: 15 Function: 0 Offset: 11Ch Bit Attr Reset Value 31:24 RV 0h Reserved Bh MH1_2ND_CHN_ASTN MemHot[1]# 2nd Channel Association bit 23 is valid bit. Note: Valid bit means the association is valid and it does not imply the channel is populated. bit 22-20 = 2nd channel ID within this MEMHOT domain. Note: This register is hardcoded in design.
Processor Uncore Configuration Registers 4.2.7.6 MH_TEMP_STAT—MEMHOT Temperature Status Register MH_TEMP_STAT Bus: 1 Bit Function: 0 Offset: 120h Reset Value Description 31 RW-V 0h MH1_DIMM_VAL Valid if set. PCODE searches the hottest DIMM temperature and writes the hottest temperature and the corresponding Hottest DIMM CID/ID and sets the valid bit. MEMHOT hardware logic processes the corresponding MEMHOT data when there is a MEMHOT event. Upon processing, the valid bit is reset.
Processor Uncore Configuration Registers 4.2.7.7 MH_EXT_STAT Register Capture externally asserted MEM_HOT[1:0]# assertion detection. MH_EXT_STAT Bus: 1 Device: 15 Function: 0 Offset: 124h Bit Attr Reset Value 31:2 RV 0h Reserved 0b MH_EXT_STAT_1 MEM_HOT[1]# assertion status at this sense period. Set if MEM_HOT[1]# is asserted externally for this sense period. This running status bit will automatically update with the next sensed value in the next MEM_HOT input sense phase.
Processor Uncore Configuration Registers SMB_STAT_[0:1] Bus: 1 Device: 15 Bit Offset: 180h Reset Value Description 28 ROS-V 0h SMB_BUSY: SMBus Busy state This bit is set by iMC while an SMBus/I2C command (including TSOD command issued from IMC hardware) is executing. Any transaction that is completed normally or gracefully will clear this bit automatically. By setting the SMB_SOFT_RST will also clear this bit.
Processor Uncore Configuration Registers 4.2.8.2 SMBCMD_[0:1]—SMBus Command Register A write to this register initiates a DIMM EEPROM access through the SMBus/I2C*. SMBCMD_[0:1] Bus: 1 Bit 31 Attr RW-V Device: 15 Function: 0 Offset: 184h Reset Value Description 0b SMB_CMD_TRIGGER: CMD Trigger After setting this bit to 1, the SMBus master will issue the SMBus command using the other fields written in SMBCMD_[0:1] and SMBCntl_[0:1].
Processor Uncore Configuration Registers 4.2.8.3 SMBCntl_[0:1]—SMBus Control Register SMBCntl_[0:1] Bus: 1 Bit 31:28 27 350 Attr RWS RWS-V Device: 15 Function: 0 Offset: 188h Reset Value Description 1010b SMB_DTI: Device Type Identifier This field specifies the device type identifier. Only devices with this device-type will respond to commands. 0011 = Specifies TSOD. 1010 = Specifies EEPROMs. 0110 = Specifies a write-protect operation for an EEPROM.
Processor Uncore Configuration Registers SMBCntl_[0:1] Bus: 1 Bit 8 7:0 4.2.8.4 Attr RW-LB RW-LB Device: 15 Function: 0 Offset: 188h Reset Value Description 0h SMB_TSOD_POLL_EN: TSOD Polling Enable 0 = Disable TSOD polling and enable SPDCMD accesses. 1 = Disable SPDCMD access and enable TSOD polling. It is important to make sure no pending SMBus transaction and the TSOD polling must be disabled (and pending TSOD polling must be drained) before changing the TSODPOLLEN.
Processor Uncore Configuration Registers 4.2.8.5 SMB_STAT_1—SMBus Status Register This register provides the interface to the SMBus/I2C (SCL and SDA signals) that is used to access the Serial Presence Detect EEPROM or Thermal Sensor on DIMM (TSOD) that defines the technology, configuration, and speed of the DIMMs controlled by iMC.
Processor Uncore Configuration Registers SMB_STAT_1 Bus: 1 Bit 15:0 4.2.8.6 Attr RO-V Device: 15 Function: 0 Offset: 190h Reset Value Description 0000h SMB_RDATA: Read Data Holds data read from SMBus Read commands. Since TSOD/EEPROM are I2C devices and the byte order is MSByte first in a word read, reading of I2C using word read should return SMB_RDATA[15:8]=I2C_MSB and SMB_RDATA[7:0]=I2C_LSB. If reading of I2C using byte read, the SMB_RDATA[15:8]=donít care; SMB_RDATA[7:0]=read_byte.
Processor Uncore Configuration Registers SMBCMD_1 Bus: 1 Bit 15:0 4.2.8.7 Attr RWS Function: 0 Offset: 194h Reset Value Description 0000h SMB_WDATA: Write Data Holds data to be written by SPDW commands. Since TSOD/EEPROM are I2C devices and the byte order is MSByte first in a word write, writing of I2C using word write should use SMB_WDATA[15:8]=I2C_MSB and SMB_WDATA[7:0]=I2C_LSB. If writing of I2C using byte write, the SMB_WDATA[15:8]=donít care; SMB_WDATA[7:0]=write_byte.
Processor Uncore Configuration Registers SMBCntl_1 Bus: 1 Bit Function: 0 Reset Value Offset: 198h Description 10 RW 0h SMB_SOFT_RST SMBus software reset strobe to graceful terminate pending transaction (after ACK) and keep the SMB from issuing any transaction until this bit is cleared. If slave device is hung, software can write this bit to 1 and the SMB_CKOVRD to 0 (for more than 35ms) to force hung the SMB slaves to time-out and put it in idle state without using power good reset or warm reset.
Processor Uncore Configuration Registers 4.2.8.9 SMB_PERIOD_CFG—SMBus Clock Period Config Register SMB_PERIOD_CFG Bus: 1 Device: 15 Bit 15:0 4.2.8.10 Attr RWS Description 0FA0h SMB_CLK_PRD This field specifies both SMBus Clock in number of DCLK. Note: To generate a 50% duty cycle SCL, half of the SMB_CLK_PRD is used to generate SCL high. SCL must stay low for at least another half of the SMB_CLK_PRD before pulling high.
Processor Uncore Configuration Registers 4.2.9 Integrated Memory Controller DIMM Memory Technology Type Registers 4.2.9.
Processor Uncore Configuration Registers 4.2.9.2 DIMMMTR_[0:2]—DIMM Memory Technology Register DIMMMTR_[0:2] Bus: 1 Bus: 1 Bus: 1 Bus: 1 15 15 15 15 Bit Attr Reset Value 31:20 RV 0h Reserved Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 80h, 80h, 80h, 80h, 84h, 84h, 84h, 84h, 88h 88h 88h 88h Description 19:16 RW-LB 0h RANK_DISABLE Control RANK Disable Control to disable patrol, refresh, and ZQCAL operation.
Processor Uncore Configuration Registers 4.2.10 Integrated Memory Controller Memory Target Address Decoder Registers 4.2.10.
Processor Uncore Configuration Registers 4.2.11 Integrated Memory Controller Channel Rank Registers There are a total of 6 RIR ranges (represents how many rank interleave ranges supported to cover DIMM configuration). 4.2.11.1 RIRWAYNESSLIMIT_[0:4]—RIR Range Wayness and Limit Register RIRWAYNESSLIMIT_[0:4] Bus: 1 Device: 15 Bus: 1 Device: 15 Bus: 1 Device: 15 Bus: 1 Device: 15 4.2.11.
Processor Uncore Configuration Registers 4.2.11.3 RIRILV1OFFSET_[0:4]—RIR Range Rank Interleave 1 OFFSET Register RIRILV1OFFSET_[0:4] Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.11.4 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 124h 124h 124h 124h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW 0h RIR_RNK_TGT1 Target rank ID for rank interleave 1 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.11.5 RIRILV3OFFSET_[0:4]—RIR Range Rank Interleave 3 OFFSET Register RIRILV3OFFSET_[0:4] Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.11.6 2 3 4 5 Offset: Offset: Offset: Offset: 12Ch 12Ch 12Ch 12Ch Attr Reset Value 31:20 RV 0h Reserved 19:16 RW 0h RIR_RNK_TGT3 Target rank ID for rank interleave 3 (used for 1/2/4/8-way RIR interleaving). 15 RV 0h Reserved Description 14:2 RW 0h RIR_OFFSET3 RIR[5:0].
Processor Uncore Configuration Registers RIRILV5OFFSET_[0:4] Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.11.8 Bit Attr Reset Value 1:0 RV 0h Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 134h 134h 134h 134h Description Reserved RIRILV6OFFSET_[0:4]—RIR Range Rank Interleave 6 OFFSET Register RIRILV6OFFSET_[0:4] Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.11.
Processor Uncore Configuration Registers 4.2.11.10 RIRILV0OFFSET_1—RIR Range Rank Interleave 0 OFFSET Register RIRILV0OFFSET_1 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.11.11 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 140h 140h 140h 140h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW 0h RIR_RNK_TGT0 Target rank ID for rank interleave 0 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.11.12 RIRILV2OFFSET_1—RIR Range Rank Interleave 2 OFFSET Register RIRILV2OFFSET_1 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.11.13 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 148h 148h 148h 148h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW 0h RIR_RNK_TGT2 Target rank ID for rank interleave 2 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.11.14 RIRILV4OFFSET_1—RIR Range Rank Interleave 4 OFFSET Register RIRILV4OFFSET_1 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.11.15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 150h 150h 150h 150h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW 0h RIR_RNK_TGT4 Target rank ID for rank interleave 4 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.11.16 RIRILV6OFFSET_1—RIR Range Rank Interleave 6 OFFSET Register RIRILV6OFFSET_1 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.11.17 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 158h 158h 158h 158h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW 0h RIR_RNK_TGT6 Target rank ID for rank interleave 6 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.11.18 RIRILV0OFFSET_2—RIR Range Rank Interleave 0 OFFSET Register RIRILV0OFFSET_2 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.11.19 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 160h 160h 160h 160h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW 0h RIR_RNK_TGT0 Target rank ID for rank interleave 0 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.11.20 RIRILV2OFFSET_2—RIR Range Rank Interleave 2 OFFSET Register RIRILV2OFFSET_2 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.11.21 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 168h 168h 168h 168h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW 0h RIR_RNK_TGT2 Target rank ID for rank interleave 2 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.11.22 RIRILV4OFFSET_2—RIR Range Rank Interleave 4 OFFSET Register RIRILV4OFFSET_2 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.11.23 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 170h 170h 170h 170h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW 0h RIR_RNK_TGT4 Target rank ID for rank interleave 4 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.11.24 RIRILV6OFFSET_2—RIR Range Rank Interleave 6 OFFSET Register RIRILV6OFFSET_2 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.11.25 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 178h 178h 178h 178h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW 0h RIR_RNK_TGT6 Target rank ID for rank interleave 6 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.11.26 RIRILV0OFFSET_3—RIR Range Rank Interleave 0 OFFSET Register RIRILV0OFFSET_3 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.11.27 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 180h 180h 180h 180h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW 0h RIR_RNK_TGT0 Target rank ID for rank interleave 0 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.11.28 RIRILV2OFFSET_3—RIR Range Rank Interleave 2 OFFSET Register RIRILV2OFFSET_3 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.11.29 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 188h 188h 188h 188h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW 0h RIR_RNK_TGT2 Target rank ID for rank interleave 2 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.11.30 RIRILV4OFFSET_3—RIR Range Rank Interleave 4 OFFSET Register RIRILV4OFFSET_3 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.11.31 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 190h 190h 190h 190h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW 0h RIR_RNK_TGT4 Target rank ID for rank interleave 4 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.11.32 RIRILV6OFFSET_3—RIR Range Rank Interleave 6 OFFSET Register RIRILV6OFFSET_3 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.11.33 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 198h 198h 198h 198h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW 0h RIR_RNK_TGT6 Target rank ID for rank interleave 6 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.11.34 RIRILV0OFFSET_4—RIR Range Rank Interleave 0 OFFSET Register RIRILV0OFFSET_4 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.11.35 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 1A0h 1A0h 1A0h 1A0h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW 0h RIR_RNK_TGT0 Target rank ID for rank interleave 0 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.11.36 RIRILV2OFFSET_4—RIR Range Rank Interleave 2 OFFSET Register RIRILV2OFFSET_4 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.11.37 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 1A8h 1A8h 1A8h 1A8h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW 0h RIR_RNK_TGT2 Target rank ID for rank interleave 2 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.11.38 RIRILV4OFFSET_4—RIR Range Rank Interleave 4 OFFSET Register RIRILV4OFFSET_4 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.11.39 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 1B0h 1B0h 1B0h 1B0h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW 0h RIR_RNK_TGT4 Target rank ID for rank interleave 4 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.11.40 RIRILV6OFFSET_4—RIR Range Rank Interleave 6 OFFSET Register RIRILV6OFFSET_4 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.11.41 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 1B8h 1B8h 1B8h 1B8h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW 0h RIR_RNK_TGT6 Target rank ID for rank interleave 6 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12 Integrated Memory Controller Error Injection Registers Complete address match (Addr[45:3]) and mask is supported for all Home Agent writes. Error injection does not use the response logic triggers and uses the match mask logic output to determine which writes need to get error injection. Users can program up to two x4 device masks (8-bits per chunk - 64 bits per cacheline). 4.2.12.
Processor Uncore Configuration Registers 4.2.12.3 RIRILV0OFFSET_[0:4]—RIR Range Rank Interleave 0 OFFSET Register RIRILV0OFFSET_[0:4] Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.12.4 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 120h 120h 120h 120h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT0 Target rank ID for rank interleave 0 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12.5 RIRILV2OFFSET_[0:4]—RIR Range Rank Interleave 2 OFFSET Register RIRILV2OFFSET_[0:4] Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.12.6 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 128h 128h 128h 128h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT2 Target rank ID for rank interleave 2 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12.7 RIRILV4OFFSET_[0:4]—RIR Range Rank Interleave 4 OFFSET Register RIRILV4OFFSET_[0:4] Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.12.8 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 130h 130h 130h 130h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT4 Target rank ID for rank interleave 4 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12.9 RIRILV6OFFSET_[0:4]—RIR Range Rank Interleave 6 OFFSET Register RIRILV6OFFSET_[0:4] Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.12.10 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 138h 138h 138h 138h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT6 Target rank ID for rank interleave 6 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12.11 RIRILV0OFFSET_1—RIR Range Rank Interleave 0 OFFSET Register RIRILV0OFFSET_1 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.12.12 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 140h 13Ch 13Ch 13Ch Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT0 Target rank ID for rank interleave 0 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12.13 RIRILV2OFFSET_1—RIR Range Rank Interleave 2 OFFSET Register RIRILV2OFFSET_1 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.12.14 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 148h 148h 148h 148h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT2 Target rank ID for rank interleave 2 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12.15 RIRILV4OFFSET_1—RIR Range Rank Interleave 4 OFFSET Register RIRILV4OFFSET_1 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.12.16 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 150h 150h 150h 150h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT4 Target rank ID for rank interleave 4 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12.17 RIRILV6OFFSET_1—RIR Range Rank Interleave 6 OFFSET Register RIRILV6OFFSET_1 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.12.18 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 158h 158h 158h 158h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT6 Target rank ID for rank interleave 6 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12.19 RIRILV0OFFSET_2—RIR Range Rank Interleave 0 OFFSET Register RIRILV0OFFSET_2 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.12.20 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 160h 15Ch 15Ch 15Ch Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT0 Target rank ID for rank interleave 0 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12.21 RIRILV2OFFSET_2—RIR Range Rank Interleave 2 OFFSET Register RIRILV2OFFSET_2 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.12.22 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 168h 168h 168h 168h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT2 Target rank ID for rank interleave 2 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12.23 RIRILV4OFFSET_2—RIR Range Rank Interleave 4 OFFSET Register RIRILV4OFFSET_2 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.12.24 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 170h 170h 170h 170h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT4 Target rank ID for rank interleave 4 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12.25 RIRILV6OFFSET_2—RIR Range Rank Interleave 6 OFFSET Register RIRILV6OFFSET_2 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 392 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 178h 178h 178h 178h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT6 Target rank ID for rank interleave 6 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12.26 RIRILV7OFFSET_2—RIR Range Rank Interleave 7 OFFSET Register RIRILV7OFFSET_2 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.12.27 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 17Ch 17Ch 17Ch 17Ch Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT7 Target rank ID for rank interleave 7 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12.28 RIRILV1OFFSET_3—RIR Range Rank Interleave 1 OFFSET Register RIRILV1OFFSET_3 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.12.29 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 184h 184h 184h 184h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT1 Target rank ID for rank interleave 1 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12.30 RIRILV3OFFSET_3—RIR Range Rank Interleave 3 OFFSET Register RIRILV3OFFSET_3 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.12.31 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 18Ch 18Ch 18Ch 18Ch Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT3 Target rank ID for rank interleave 3 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12.32 RIRILV5OFFSET_3—RIR Range Rank Interleave 5 OFFSET Register RIRILV5OFFSET_3 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.12.33 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 194h 194h 194h 194h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT5 Target rank ID for rank interleave 5 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12.34 RIRILV7OFFSET_3—RIR Range Rank Interleave 7 OFFSET Register RIRILV7OFFSET_3 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.12.35 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 19Ch 19Ch 19Ch 19Ch Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT7 Target rank ID for rank interleave 7 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12.36 RIRILV1OFFSET_4—RIR Range Rank Interleave 1 OFFSET Register RIRILV1OFFSET_4 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.12.37 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 1A4h 1A4h 1A4h 1A4h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT1 Target rank ID for rank interleave 1 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12.38 RIRILV3OFFSET_4—RIR Range Rank Interleave 3 OFFSET Register RIRILV3OFFSET_4 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.12.39 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 1ACh 1ACh 1ACh 1ACh Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT3 Target rank ID for rank interleave 3 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12.40 RIRILV5OFFSET_4—RIR Range Rank Interleave 5 OFFSET Register RIRILV5OFFSET_4 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.12.41 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 1B4h 1B4h 1B4h 1B4h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT5 Target rank ID for rank interleave 5 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12.42 RIRILV7OFFSET_4—RIR Range Rank Interleave 7 OFFSET Register RIRILV7OFFSET_4 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.12.43 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 1BCh 1BCh 1BCh 1BCh Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT7 Target rank ID for rank interleave 7 (used for 1/2/4/8-way RIR interleaving).
Processor Uncore Configuration Registers 4.2.12.44 RSP_FUNC_ADDR_MATCH_HI Register Complete address match (Addr[45:3]) and mask is supported for all HA writes. Instead of using DFx global response logic triggers, the error injection logic uses the address match mask logic output to determine which memory writes need to get error injection. Users can program up to two x4 device masks (8-bits per chunk – 64 bits per cacheline).
Processor Uncore Configuration Registers 4.2.12.46 RSP_FUNC_ADDR_MASK_HI Register Complete address match (Addr[45:3]) and mask is supported for all HA writes. Error injection does not use the response logic triggers and uses the match mask logic output to determine which writes need to get error injection. Users can program up to two x4 device masks (8-bits per chunk – 64 bits per cacheline). The address match function is gated by EPMCMAIN_DFX_LCK_CNTL.RSPLCK (uCR) AND MC_ERR_INJ_LCK.
Processor Uncore Configuration Registers 4.2.13.
Processor Uncore Configuration Registers 4.2.13.3 CHN_TEMP_CFG—Channel TEMP Configuration Register CHN_TEMP_CFG Bus: 1 Bus: 1 Bus: 1 Bus: 1 4.2.13.
Processor Uncore Configuration Registers 4.2.13.
Processor Uncore Configuration Registers 4.2.13.
Processor Uncore Configuration Registers 4.2.13.7 DIMM_TEMP_THRT_LMT_[0:2]—DIMM TEMP Configuration Register All three THRT_CRIT, THRT_HI and THRT_MID are per DIMM BW limit; that is, all activities (ACT, READ, WRITE) from all ranks within a DIMM are tracked together in one DIMM activity counter.
Processor Uncore Configuration Registers 4.2.13.8 DIMM_TEMP_EV_OFST_[0:2]—DIMM TEMP Configuration Register DIMM_TEMP_EV_OFST_[0:2] Bus: 1 Device: 16 Bus: 1 Device: 16 Bus: 1 Device: 16 Bus: 1 Device: 16 Bit Attr Function: Function: Function: Function: 0 1 4 5 Offset: Offset: Offset: Offset: 140h, 140h, 140h, 140h, 144h, 144h, 144h, 144h, 148h 148h 148h 148h Reset Value Description TEMP_AVG_INTRVL Temperature data is averaged over this period.
Processor Uncore Configuration Registers 4.2.13.
Processor Uncore Configuration Registers 4.2.13.
Processor Uncore Configuration Registers 4.2.13.
Processor Uncore Configuration Registers 4.2.13.13 THRT_PWR_DIMM_[0:2]—THRT_PWR_DIMM_0 Register bit[10:0]: Max number of transactions (ACT, READ, WRITE) to be allowed during the 1 usec throttling time frame per power throttling.
Processor Uncore Configuration Registers PM_PDWN Bus: 1 Bus: 1 Bus: 1 Bus: 1 Bit 16 16 16 16 Function: Function: Function: Function: 0 1 4 5 Offset: Offset: Offset: Offset: 1D0h 1D0h 1D0h 1D0h Reset Value Description Power Down Clock Modes for UDIMM The field defines how CK and CK# are turned off during SR: 00 = CK_ON Mode: This mode defines the CK to be continue to be driven during self-refresh.
Processor Uncore Configuration Registers 4.2.13.15 MC_TERM_RNK_MSK—MC Termination Rank Mask Register MC_TERM_RNK_MSK Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bit Attr Reset Value 31:16 RW 01FFh 15:10 RV 0h 9:0 4.2.13.16 RW 111h 16 16 16 16 Function: Function: Function: Function: 0 1 4 5 Offset: Offset: Offset: Offset: 1D4h 1D4h 1D4h 1D4h Description ch_ppds_idle_timer PPDS idle counter after all rank’s rank idle counters (PDWN_IDEL_CNTR) have been expired.
Processor Uncore Configuration Registers 4.2.13.17 PM_DLL—PM DLL Config Register This register controls the master and slave DLL of the MC I/O. The slave DLL, if configured to disable, is disabled when all ranks are in power-down. The master DLL, if configured to disable, is disabled when self-refresh. Both slave DLL and master DLL have wake-up time. Slave DLL disable has wake-up time of ~50 ns, and master DLL wake-up time is ~500 ns.
Processor Uncore Configuration Registers 4.2.13.18 ET_CH_AVG—Electrical Throttling Energy Averager Register ET_CH_AVG Bus: 1 Bus: 1 Bus: 1 Bus: 1 4.2.13.
Processor Uncore Configuration Registers 4.2.14 Integrated Memory Controller DIMM Channels Timing Registers 4.2.14.1 TCDBP—Timing Constraints DDR3 Bin Parameter Register Note: T_AL register field has been removed in this release due to design complexity. Throughout this document, T_AL has a constant zero value.
Processor Uncore Configuration Registers 4.2.14.2 TCRAP—Timing Constraints DDR3 Regular Access Parameter Register TCRAP Bus: 1 Bus: 1 Bus: 1 Bus: 1 Bit Device: Device: Device: Device: Attr 16 16 16 16 Reset Value Function: Function: Function: Function: 0 1 4 5 Offset: Offset: Offset: Offset: 204h 204h 204h 204h Description 31:30 RW 0h CMD_STRETCH This field defines the number of cycles the command is stretched.
Processor Uncore Configuration Registers 4.2.14.3 TCRWP—Timing Constraints DDR3 Read Write Parameter Register TCRWP Bus: 1 Bus: 1 Bus: 1 Bus: 1 16 16 16 16 Bit Attr Reset Value 31:30 RV 0h Reserved Function: Function: Function: Function: 0 1 4 5 Offset: Offset: Offset: Offset: 208h 208h 208h 208h Description 29:27 RW 0h T_CCD Back to back CAS to CAS (that is, READ to READ or WRITE to WRITE) from same rank separation parameter.
Processor Uncore Configuration Registers TCRWP Bus: 1 Bus: 1 Bus: 1 Bus: 1 Bit 2:0 Datasheet, Volume 2 Device: Device: Device: Device: Attr RW 16 16 16 16 Function: Function: Function: Function: 0 1 4 5 Offset: Offset: Offset: Offset: 208h 208h 208h 208h Reset Value Description 2h T_RRDR Back to back READ to READ from different RANK separation parameter.
Processor Uncore Configuration Registers 4.2.14.4 TCOTHP—Timing Constraints DDR3 Other Timing Parameter Register TCOTHP Bus: 1 Bus: 1 Bus: 1 Bus: 1 16 16 16 16 Function: Function: Function: Function: 0 1 4 5 Offset: Offset: Offset: Offset: 20Ch 20Ch 20Ch 20Ch Bit Attr Reset Value 31:28 RW 6h t_cs_oe Delay in Dclks to disable CS output after all CKE pins are low.
Processor Uncore Configuration Registers 4.2.14.5 TCRFP—Timing Constraints DDR3 Refresh Parameter Register TCRFP Bus: 1 Bus: 1 Bus: 1 Bus: 1 4.2.14.
Processor Uncore Configuration Registers 4.2.14.7 TCSRFTP—Timing Constraints Self-Refresh Timing Parameter Register TCSRFTP Bus: 1 Bus: 1 Bus: 1 Bus: 1 4.2.14.8 Device: Device: Device: Device: Function: Function: Function: Function: 0 1 4 5 Offset: Offset: Offset: Offset: 218h 218h 218h 218h Bit Attr Reset Value 31:27 RW ch T_MOD Mode Register Set command update delay.
Processor Uncore Configuration Registers TCMR2SHADOW Bus: 1 Bus: 1 Bus: 1 Bus: 1 Bit 4.2.14.9 Attr Device: Device: Device: Device: 16 16 16 16 Function: Function: Function: Function: 0 1 4 5 Offset: Offset: Offset: Offset: 21Ch 21Ch 21Ch 21Ch Reset Value Description MR2_SHDW_A7_SRT Copy of MR2 A[7] shadow that defines per DIMM availability of SRT mode – set if extended temperature range and ASR is not supported; otherwise, cleared.
Processor Uncore Configuration Registers 4.2.14.10 TCSTAGGER_REF Register This register provides the tRFC like timing constraint parameter except it is a timing constraint applicable to REF-REF separation between different ranks on a channel. Note: This register value only becomes effective after MCMNT_UCR_CHKN_BIT.STAGGER_REF_EN is set. TCSTAGGER_REF Bus: 1 Bus: 1 Bus: 1 Bus: 1 Bit Attr Reset Value 31:10 RV 0h 9:0 4.2.14.
Processor Uncore Configuration Registers 4.2.14.12 RPQAGE Register This register allows the Read of Pending Queue Age Counters. RPQAGE Bus: 1 Bus: 1 Bus: 1 Bus: 1 Bit Attr Reset Value 31:26 RV 0h 25:16 RW 000h 15:10 RV 0h 9:0 4.2.14.13 Device: Device: Device: Device: RW 000h 16 16 16 16 Function: Function: Function: Function: 0 1 4 5 Offset: Offset: Offset: Offset: 234h 234h 234h 234h Description Reserved IOCount The name is misleading.
Processor Uncore Configuration Registers IDLETIME Bus: 1 Bus: 1 Bus: 1 Bus: 1 4.2.14.14 Device: Device: Device: Device: Function: Function: Function: Function: 0 1 4 5 Offset: Offset: Offset: Offset: 238h 238h 238h 238h Bit Attr Reset Value 27:21 RW 06h OPC_TH: Overdue Page Close (OPC) Threshold If the number of OPCs in a given window is larger than this threshold, The RV is decreased.
Processor Uncore Configuration Registers 4.2.14.15 RDIMMTIMINGCNTL2 Register RDIMMTIMINGCNTL2 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 0 1 4 5 Offset: Offset: Offset: Offset: 240h 240h 240h 240h Attr Reset Value 31:8 RV 0h Reserved 5h T_CKOFF This field provides the tCKOFF timing parameter. The number of tCK required for both DCKE0 and DCKE1 to remain LOW before both CK/CK# are driven Low. Minimum setting is 2.
Processor Uncore Configuration Registers RD_ODT_TBL0 Bus: 1 Bus: 1 Bus: 1 Bus: 1 4.2.14.18 Device: Device: Device: Device: 16 16 16 16 Function: Function: Function: Function: Bit Attr Reset Value 13:8 RW 0h RD_ODT_RANK1 Rank 1 Read ODT pins 7:6 RV 0h Reserved 5:0 RW 0h RD_ODT_RANK0 Rank 0 Read ODT pins 0 1 4 5 Offset: Offset: Offset: Offset: 260h 260h 260h 260h Description RD_ODT_TBL1—Read ODT Lookup Table 1 Register One entry for each physical rank on each channel.
Processor Uncore Configuration Registers 4.2.14.19 RD_ODT_TBL2—Read ODT Lookup Table 2 Register One entry for each physical rank on each channel. Each entry defines which ODT signals are asserted when accessing that rank. This register also includes ODT timing control. The recommended BIOS settings to keep the MC_TERM_RNK_MSK consistent are: • Set Read ODT mapping – read ODT specifies all ODT pins assertion for a read targeting at this rank. Please clear read target DIMM's termination rank bit.
Processor Uncore Configuration Registers 4.2.14.20 WR_ODT_TBL0—Write ODT Lookup Table 0 Register One entry for each physical rank on each channel. Each entry defines which ODT signals are asserted when accessing that rank. This register also includes ODT timing control. The recommended BIOS settings to keep the MC_TERM_RNK_MSK consistent are: • Set Write ODT mapping - write ODT specified all ODT pins assertion for a write targeting at this rank. All DIMM's termination rank must have the ODT mask asserted.
Processor Uncore Configuration Registers 4.2.14.21 WR_ODT_TBL1—Write ODT Lookup Table 1 Register One entry for each physical rank on each channel. Each entry defines which ODT signals are asserted when accessing that rank. This register also includes ODT timing control. The recommended BIOS settings to keep the MC_TERM_RNK_MSK consistent are: • Set Write ODT mapping – write ODT specified all ODT pins assertion for a write targeting at this rank.
Processor Uncore Configuration Registers 4.2.14.22 WR_ODT_TBL2—Write ODT Lookup Table 2 Register One entry for each physical rank on each channel. Each entry defines which ODT signals are asserted when accessing that rank. This register also includes ODT timing control. The recommended BIOS settings to keep the MC_TERM_RNK_MSK consistent are: • Set Write ODT mapping – write ODT specified all ODT pins assertion for a write targeting at this rank. All DIMM's termination rank must have the ODT mask asserted.
Processor Uncore Configuration Registers 4.2.14.24 RSP_FUNC_MCCTRL_ERR_INJ Register Error Injection Response Function This register is locked by EPMCMAIN_DFX_LCK_CNTL.RSPLCK (uCR) AND MC_ERR_INJ_LCK.MC_ERR_INJ_LCK (MSR). The referenced Used Trigger-0/Use Trigger-1/Use Trigger-2 are being mapped as the followings: • 01 - Use Trigger-0 from MCGLBRSPCNTL.GlbRsp0 • 10 - Use Trigger-1 from MCGLBRSPCNTL.GlbRsp1 • 11 - Use Trigger-2 from MCGLBRSPCNTL.
Processor Uncore Configuration Registers 4.2.14.26 WDBWM—WDB Watermarks Register This register configures the WMM behavior – watermarks and the starvation counter. Setup rules that must be kept are: • 1 WMM_EXIT < WMM_ENTER - 1 • WMM_ENTER < WPQ_IS • RPQ_SIZE + 5 WPQ_IS • WPQ_IS max value is 29 WDBWM Bus: 1 Bus: 1 Bus: 1 Bus: 1 4.2.14.
Processor Uncore Configuration Registers 4.2.14.28 SPARING Register This is the Sparing Credit register SPARING Bus: 1 Bus: 1 Bus: 1 Bus: 1 Device: Device: Device: Device: Bit Attr Reset Value 31:14 RV 0h 13:8 RW 05h 7:6 RV 0h 5:0 RW 00h 16 16 16 16 Function: Function: Function: Function: 0 1 4 5 Offset: Offset: Offset: Offset: 338h 338h 338h 338h Description Reserved WRFIFOHWM This field provides the maximum number of merged write isoch transactions allowed in a channel.
Processor Uncore Configuration Registers 4.2.15.2 IOSAV_CH_ADDR_UPDT_[0:3]—IOSAV Channel Address Update Seq 0 Register Need to accommodate slot increment The RW-L field is locked by either NORMAL bit in MCMTR register or by IOSAV_DISABLE bit in LT_IOSAV_MEMINIT_DIS register.
Processor Uncore Configuration Registers 4.2.15.3 IOSAV_CH_ADDR_LFSR_[0:3]— IOSAV Channel Address LFSR Seq 0 Register The RW-L field is locked by either NORMAL bit in MCMTR register or by IOSAV_DISABLE bit in LT_IOSAV_MEMINIT_DIS register. IOSAV_CH_ADDR_LFSR_[0:3] Bus: 1 Device: 16 Bus: 1 Device: 16 Bus: 1 Device: 16 Bus: 1 Device: 16 4.2.15.
Processor Uncore Configuration Registers IOSAV_CH_SPCL_CMD_CTRL_[0:3] Bus: 1 Device: 16 Bus: 1 Device: 16 Bus: 1 Device: 16 Bus: 1 Device: 16 Bit 4.2.15.
Processor Uncore Configuration Registers 4.2.15.6 IOSAV_CH_SEQ_CTRL—IOSAV Channel Sequence Control Register The RW-L field is locked by either NORMAL bit in MCMTR register or by IOSAV_DISABLE bit in LT_IOSAV_MEMINIT_DIS register.
Processor Uncore Configuration Registers 4.2.15.7 IOSAV_CH_STAT—IOSAV Channel Status Register This register is cleared when writing to the REPEAT field of IOSAV_CH_SEQ_CTRL. IOSAV_CH_STAT Bus: 1 Bus: 1 Bus: 1 Bus: 1 16 16 16 16 Bit Attr Reset Value 31:8 RV 0h Reserved Function: Function: Function: Function: 0 1 4 5 Offset: Offset: Offset: Offset: 454h 454h 454h 454h Description 7 RO-V 0b DONE_AND_REF_DRAINED This bit is cleared with the Idle-done bit when a new sequence is written.
Processor Uncore Configuration Registers 4.2.15.8 IOSAV_CH_DATA_CNTL—IOSAV Channel Data Control Register This register controls the data flow. This register is read & write, but it is should not be written while a sequence is active (doing this shall cause unpredictable results). The RW-L field is locked by either NORMAL bit in MCMTR register or by IOSAV_DISABLE bit in LT_IOSAV_MEMINIT_DIS register.
Processor Uncore Configuration Registers 4.2.16 Integrated Memory Controller Error Registers 4.2.16.1 ROUNDTRIP0—Round-Trip Latency Register ROUNDTRIP0 Bus: 1 Bus: 1 Bus: 1 Bus: 1 4.2.16.
Processor Uncore Configuration Registers 4.2.16.3 IOLATENCY0—IO Latency Register IOLATENCY0 Bus: 1 Bus: 1 Bus: 1 Bus: 1 4.2.16.
Processor Uncore Configuration Registers 4.2.16.5 WDBPRELOADREG0—WDB Data Load Register 0 WDB Data Load Register 0 Bus: 1 Device: 16 Bus: 1 Device: 16 Bus: 1 Device: 16 Bus: 1 Device: 16 4.2.16.6 2 3 6 7 Offset: Offset: Offset: Offset: Bit Attr Reset Value 31:24 RW-LB 00h XFER4 4th transfer on a byte of the DDR Bus. 23:16 RW-LB 00h XFER3 3rd transfer on a byte of the DDR Bus. 15:8 RW-LB 00h XFER2 2nd transfer on a byte of the DDR Bus.
Processor Uncore Configuration Registers 4.2.16.7 WDBPRELOADCTRL—WDB Preload Control Register The following is an example to program this register. If you want to load entry 0 with a 01010101...
Processor Uncore Configuration Registers 4.2.16.8 CORRERRCNT_0—Corrected Error Count Register This register has per Rank corrected error counters. CORRERRCNT_0 Bus: 1 Bus: 1 Bus: 1 Bus: 1 Device: Device: Device: Device: 16 16 16 16 Function: Function: Function: Function: 2 3 6 7 104h 104h 104h 104h Bit Attr Reset Value Description 31 RW1CS 0b RANK 1 OVERFLOW The corrected error count for this rank has been overflowed. Once set, it can only be cleared using a write from BIOS.
Processor Uncore Configuration Registers 4.2.16.9 CORRERRCNT_1—Corrected Error Count Register This register has per Rank corrected error counters. CORRERRCNT_1 Bus: 1 Bus: 1 Bus: 1 Bus: 1 4.2.16.10 Device: Device: Device: Device: 16 16 16 16 Function: Function: Function: Function: 2 3 6 7 Offset: Offset: Offset: Offset: 108h 108h 108h 108h Bit Attr Reset Value Description 31 RW1CS 0b RANK 3 OVERFLOW The corrected error count has crested over the limit for this rank.
Processor Uncore Configuration Registers 4.2.16.11 CORRERRCNT_3—Corrected Error Count Register This register has per Rank corrected error counters. CORRERRCNT_3 Bus: 1 Bus: 1 Bus: 1 Bus: 1 4.2.16.12 Device: Device: Device: Device: 16 16 16 16 Function: Function: Function: Function: 2 3 6 7 Offset: Offset: Offset: Offset: Bit Attr Reset Value 31 RW1CS 0b RANK 7 OVERFLOW The corrected error count for this rank. 30:16 RWS-V 0000h RANK 7 COR_ERR_CNT_7 The corrected error count for this rank.
Processor Uncore Configuration Registers 4.2.16.13 CORRERRTHRSHLD_1—Corrected Error Threshold Register This register holds the per rank corrected error thresholding value. CORRERRTHRSHLD_1 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.16.
Processor Uncore Configuration Registers 4.2.16.16 CORRERRORSTATUS—Corrected Error Status Register This register holds per rank corrected error status. These bits are reset by BIOS.
Processor Uncore Configuration Registers 4.2.16.17 LEAKY_BKT_2ND_CNTR_REG Register LEAKY_BKT_2ND_CNTR_REG Bus: 1 Device: 16 Bus: 1 Device: 16 Bit 31:16 15:0 Datasheet, Volume 2 Attr RW RW-V Function: 2 Function: 6 Offset: 138h Offset: 138h Reset Value Description 0000h LEAKY_BKT_2ND_CNTR_LIMIT Secondary Leaky Bucket Counter Limit (2b per DIMM). This register defines the secondary leaky bucket counter limit for all 8 logical ranks within channel.
Processor Uncore Configuration Registers 4.2.16.18 DEVTAG_CNTRL[0:7]—Device Tagging Control for Logical Rank 0 Register Usage model – When the number of correctable errors (CORRERRCNT_x) from a particular rank exceeds the corresponding threshold (CORRERRTHRSHLD_y), hardware will generate a SMI interrupt and log (and preserve) the failing device in the FailDevice field. SMM software will read the failing device on the particular rank.
Processor Uncore Configuration Registers 4.2.16.19 IOSAV_CH_B0_B3_BW_SERR Register When an error occurs on one of the data pins, the corresponding bit in this register is set. Bits may be cleared by implicit write. At the end of a sequence (or few sequences ran one after the other without clearing the register), every bit that was set means that there was at least one error in the corresponding bit in the sequence.
Processor Uncore Configuration Registers 4.2.16.21 IOSAV_CH_B8_BW_SERR Register When an error occurs on one of the data pins, the corresponding bit in this register is set. Bits may be cleared by implicit write. At the end of a sequence (or few sequences ran one after the other without clearing the register), every bit that was set means that there was at least one error in the corresponding bit in the sequence.
Processor Uncore Configuration Registers 4.2.16.23 IOSAV_CH_B4_B7_BW_MASK Register IOSAV bit-wise compare mask registers – Each bit, if set, blocks the corresponding data bit compare. IOSAV_CH_B4_B7_BW_MASK Bus: 1 Device: 16 Bus: 1 Device: 16 Bus: 1 Device: 16 Bus: 1 Device: 16 4.2.16.
Processor Uncore Configuration Registers 4.2.16.25 IOSAV_DQ_LFSR[0:2] Register IOSAV_DQ_LFSR[0:2] Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bit Attr Reset Value 31:27 RW 00h 26:0 4.2.16.26 RW 000000 0h 16 16 16 16 2 6 3 7 Offset: Offset: Offset: Offset: 1C0h 1C0h 1C0h 1C0h Description NUMBITS Number of bits in the LFSR – maximum is 29 decimal. FBVEC LFSR XOR feedback tap points mask position. LFSR Example: MTLFSR.
Processor Uncore Configuration Registers 4.2.16.27 IOSAV_DQ_LFSR1 Register IOSAV_DQ_LFSR1 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bit Attr Reset Value 31:27 RW 0h 26:0 4.2.16.28 RW 000000 0h 16 16 16 16 Function: Function: Function: Function: 2 6 3 7 Offset: Offset: Offset: Offset: 1C8h 1C8h 1C8h 1C8h Description NUMBITS Number of bits in the LFSR – maximum is 29 decimal. FBVEC LFSR XOR feedback tap points mask position.LFSR Example: MTLFSR.
Processor Uncore Configuration Registers 4.2.16.29 IOSAV_DQ_LFSR2 Register IOSAV_DQ_LFSR2 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bit Attr Reset Value 31:27 RW 0h 26:0 4.2.16.30 RW 000000 0h Function: Function: Function: Function: 2 6 3 7 Offset: Offset: Offset: Offset: 1D0h 1D0h 1D0h 1D0h Description NUMBITS Number of bits in the LFSR – maximum is 29 decimal. FBVEC LFSR XOR feedback tap points mask position.LFSR Example: MTLFSR.
Processor Uncore Configuration Registers 4.2.16.31 MCSCRAMBLECONFIG—Data Scrambler Configuration Register This register is used to scramble and unscramble the MC to DDR Pad data using the DDR command address and the scramble seed. All the fields CH_ENABLE, TX_ENABLE and RX_ENABLE must be set to 1 to enable scrambling, and must be cleared to disable scrambling. This register can only be changed in IOSAV mode before any accesses to memory.
Processor Uncore Configuration Registers 4.2.16.33 RSP_FUNC_CRC_ERR_INJ_DEV0_XOR_MSK Register Error Injection Response Function on Address Match Write Data Error Injection. Associating registers: RSP_FUNC_ADDR_MATCH_LO&HI, RSP_FUNC_ADDR_MATCH_LO&HI, RSP_FUNC_CRC_ERR_INJ_EXTRA.CRC_ERR_INJ_DEV0_5_BITS and CRC_ERR_INJ_DEV1_5_BITS RSP_FUNC_CRC_ERR_INJ_DEV0_XOR_MSK Bus: 1 Device: 16 Function: Bus: 1 Device: 16 Function: Bus: 1 Device: 16 Function: Bus: 1 Device: 16 Function: 4.2.16.
Processor Uncore Configuration Registers 4.2.16.35 RSP_FUNC_CRC_ERR_INJ_EXTRA Register This register is provides the Error Injection Response Function.
Processor Uncore Configuration Registers 4.2.16.36 x4modesel—MDCP X4 Mode Select Register x4modesel Bus: 1 Bus: 1 Bus: 1 Bus: 1 464 Device: Device: Device: Device: 16 16 16 16 Function: Function: Function: Function: 2 3 6 7 Offset: Offset: Offset: Offset: 268h 268h 268h 268h Bit Attr Reset Value 31:3 RV 0h Reserved 2 RW 0b DIMM2_MODE Controls the DDRIO x4 (if set) / x8 (if cleared) DIMM2 DQS select.
Processor Uncore Configuration Registers 4.3 Processor Home Agent Registers 4.3.1 CSR Register Maps The following register maps are for Home Agent registers Table 4-19.
Processor Uncore Configuration Registers 4.3.2 Processor Home Agent Register The Home agent is responsible for memory transactions and interacts with the processor’s ring and handles incoming and outgoing transactions. 4.3.2.1 TMBAR—Thermal Memory Mapped Register Range Base This is the base address for the Thermal Controller Memory Mapped space. There is no physical memory within this 32 KB window that can be addressed. The 32 KB reserved by this register does not alias to any PCI 2.
Processor Uncore Configuration Registers TAD[0:11] Bus: 1 Device: 14 Function: 0 Bus: 1 Device: 14 Function: 0 Bit 9:8 4.3.2.3 Attr RWS-LB Reset Value Offset: 40h, 44h, 48h, 4Ch, 50h, 54h, 58h, 5Ch Offset: 60h, 64h, 68h, 6Ch Description 00b Number of Channel Ways This field defines the number of memory channels interleave within a socket.
Processor Uncore Configuration Registers HaCrdtCnt Bus: 1 Bit 16 15 14 13 468 Attr RW RW-V RW-V RW-V Device: 14 Function: 0 Offset: 70h Reset Value Description 0b Shared Credit Release When set, prevents schedulers from speculatively allocating shared credits in the local credit counter. This causes the idle state of the local credit counter to be zero. When cleared, shared credits are pre-allocated to both schedulers’ local counters, allowing lower latency.
Processor Uncore Configuration Registers HaCrdtCnt Bus: 1 Bit Attr Device: 14 Function: 0 Offset: 70h Reset Value Description Type of Credit to Be Accessed The HA has two schedulers. Each scheduler uses its own credit pool. The credit type 0-15 decimal are private credit types. The credit type 16-31 decimal are shared credit types.
Processor Uncore Configuration Registers 4.3.2.4 HtBase—Home Track Base Selection Register Each node has 4 bits mapping to the assigned HT segment starting address. There are 8 segments for each HT bank and total 16 segments. Each segment has 8 trackers. Two segments construct a sector. Each sector has 16 trackers. HtBase Bus: 1 Bit 470 Device: 14 Attr Reset Value Function: 0 Offset: 74h Description 31:28 RW 0000b NID7 HT Base NID7 HT Base (Nid7HtBase): This field defines the HTID mapping.
Processor Uncore Configuration Registers 4.3.2.5 HABGFTune—HA BGF Tuning Register The flow accommodates BGF sync pulse frequencies of 100 MHz, 50 MHz, 33 MHz, and 25 MHz. However, the MC frequency is likely to be a multiple of 33 MHz. The ratio would have to be programmed with respect to a 33 MHz sync pulse, and the RatioType set to use the pcode-programmed ratio exactly.
Processor Uncore Configuration Registers 4.4 Power Control Unit (PCU) Registers 4.4.1 CSR Register Maps The following register maps are for Power Control Unit registers Table 4-20.
Processor Uncore Configuration Registers Table 4-21.
Processor Uncore Configuration Registers Table 4-22.
Processor Uncore Configuration Registers Table 4-23.
Processor Uncore Configuration Registers 4.4.2 PCU0 Registers 4.4.2.1 MEM_TRML_ESTIMATION_CONFIG—Memory Thermal Estimation Configuration Register This register contains configuration regarding DDR temperature calculations that are done by PCODE. For the BW estimation mode, the following formula is used: Temperature = T(n) + AMBIENT where: T(n) = T(n-1) - (1 - Alpha) * T(n-1) + Theta * BW This register is read by PCODE only during Reset Phase 4.
Processor Uncore Configuration Registers 4.4.2.2 MEM_TRML_ESTIMATION_CONFIG2—Memory Thermal Estimation Configuration 2 Register This register is used in addition to MEM_TRML_ESTIMATION_CONFIG and will be used to set the power constant of the DDR. This register is read by PCODE only during Reset Phase 4. MEM_TRML_ESTIMATION_CONFIG2 Bus: 1 Device: 10 Function: 0 Bit Attr Reset Value 31:10 RV 0h 9:0 4.4.2.
Processor Uncore Configuration Registers 4.4.2.4 MEM_ACCUMULATED_BW_CH_[0:3]— MEM_ACCUMULATED_BW_CH_0 Register This register contains a measurement proportional to the weighted DRAM BW for the channel (including all ranks). The weights are configured in the memory controller channel register PM_CMD_PWR. MEM_ACCUMULATED_BW_CH_[0:3] Bus: 1 Device: 10 Function: 0 Bit 31:0 4.4.2.
Processor Uncore Configuration Registers PACKAGE_POWER_SKU Bus: 1 Device: 10 4.4.2.7 Bit Attr Reset Value 46:32 RO-V 0258h 31 RV 0h 30:16 RO-V 0078h 15 RV 0h 14:0 RO-V 0118h Function: 0 Offset: 84h Description Maximal Package Power The maximal package power setting allowed for the SKU. Higher values will be clamped to this value. The maximum setting is typical (not guaranteed). Reserved Minimal Package Power The minimal package power setting allowed for the SKU.
Processor Uncore Configuration Registers 4.4.2.9 PLATFORM_ID—Platform ID Register Used for selecting which patch to use. PLATFORM_ID Bus: 1 4.4.2.10 Device: 10 Bit Attr Reset Value 63:53 RV 0h 52:50 RO-V 000b 49:0 RV 0h Function: 0 Offset: A0h Description Reserved Platform ID This field contains information concerning the intended platform for the processor. Reserved PLATFORM_INFO—Platform Information Register This register contains information about platform’s frequency capabilities.
Processor Uncore Configuration Registers 4.4.2.11 PP0_Any_Thread_Activity—PP0_Any_Thread_Activity Register This register will count the BCLK cycles in which at least one of the IA cores was active. This is a 32 bit accumulation done by PCU hardware. Values exceeding 32b will wrap around. PP0_Any_Thread_Activity Bus: 1 Device: 10 4.4.2.
Processor Uncore Configuration Registers 4.4.2.14 Package_Temperature Register Package temperature in degrees (C). Package_Temperature Bus: 1 Device: 10 4.4.2.15 Bit Attr Reset Value 31:8 RV 0h 7:0 RO-V 00h Function: 0 Offset: C8h Description Reserved Temperature Package temperature in degrees C. PP0_temperature Register This register provides the PP0 temperature in degrees C. PP0_temperature Bus: 1 Device: 10 4.4.2.
Processor Uncore Configuration Registers 4.4.2.17 P_STATE_LIMITS—P-State Limits Register This register allows software to limit the maximum frequency allowed during run-time. PCODE will sample this register in slow loop. Functionality added in B-step. P_STATE_LIMITS Bus: 1 Device: 10 Function: 0 Offset: D8h Bit Attr Reset Value 31 RW-KL 0b Lock This bit will lock all settings in this register.
Processor Uncore Configuration Registers 4.4.2.18 TEMPERATURE_TARGET—Temperature Target Register This Legacy register holds temperature related constants for platform use. TEMPERATURE_TARGET Bus: 1 Device: 10 4.4.2.19 Bit Attr Reset Value 31:28 RV 0h Reserved Offset: E4h Description 27:24 RO-V 0h TJ Max TCC Offset Temperature offset in degrees (C) from the TJ Max. Used for throttling temperature. Will not impact temperature reading.
Processor Uncore Configuration Registers TURBO_POWER_LIMIT Bus: 1 Device: 10 Bit Attr Reset Value 46:32 RW-L 0000h 31:24 RV 0h 23:17 00h Offset: E8h Description Package Power Limit 2 This field indicates the power limitation #2. The unit of measurement is defined in PACKAGE_POWER_SKU_UNIT_MSR[PWR_UNIT]. Reserved Package Power Limit 1 Time Window x = PKG_PWR_LIM_1_TIME[23:22] y = PKG_PWR_LIM_1_TIME[21:17] The timing interval window is Floating Point number given by 1.x * power(2,y).
Processor Uncore Configuration Registers 4.4.2.20 PRIP_TURBO_PWR_LIM—Primary Plane Turbo Power Limitation Register This register is used by BIOS/OS/Integrated Graphics Driver/CPM Driver to limit the power budget of the Primary Power Plane. The overall package turbo power limitation is controlled by PKG_TURBO_POWER_LIMIT.
Processor Uncore Configuration Registers 4.4.2.21 PRIMARY_PLANE_CURRENT_CONFIG_CONTROL—Primary Plane Current Configuration Control Register Limitation on the maximum current consumption of the primary power plane. PCODE will read this value during Reset Phase 4. On each slow loop, PCODE will calculate the maximum current possible and send the appropriate PS Code according to the thresholds in this register.
Processor Uncore Configuration Registers 4.4.3 PCU1 Registers 4.4.3.1 SSKPD—Sticky Scratchpad Data Register This register holds 64 writable bits with no functionality behind them. It is for the convenience of BIOS and graphics drivers. SSKPD Bus: 1 4.4.3.2 Device: 10 Bit Attr Reset Value 63:0 RWS 000000 000000 0000h Function: 1 Offset: 6Ch Description Scratchpad Data 4 WORDs of data storage.
Processor Uncore Configuration Registers 4.4.3.3 PCIE_ILTR_OVRD—PCI Express* Latency Tolerance Requirement (LTR) Override Register This register includes parameters that PCODE will use to override information received from PCI Express using LTR messages. PCODE will sample this register at slow loop. PCIE_ILTR_OVRD Bus: 1 Device: 10 Function: 1 Offset: 78h Bit Attr Reset Value 31 RW 0b Snoop Latency Valid When this bit is set to 0b, PCODE will ignore the Snoop Latency override value.
Processor Uncore Configuration Registers PCIE_ILTR_OVRD Bus: 1 Device: 10 Bit 9:0 4.4.3.4 Attr RW Function: 1 Reset Value 000h Offset: 78h Description Non-Snoop Latency Value Latency requirement for Non-Snoop requests. This value is multiplied by the MULTIPLIER field to yield a time value, yielding an expressible range from 1ns to 34,326.183,936 ns.
Processor Uncore Configuration Registers 4.4.3.6 BIOS_RESET_CPL—BIOS Reset Complete Register This register is used as interface between BIOS and Pcode Bits in first Byte are written by BIOS and read by Pcode Bits in second Byte are written by Pcode and read by BIOS Expected sequence: BIOS sets RST_CPL -> Pcode sets PCODE_INIT_DONE -> BIOS sets RST_DRAM_CPL BIOS should also clear the AutoAck bit, DMICTRL.
Processor Uncore Configuration Registers BIOS_RESET_CPL Bus: 1 Device: 10 Bit 4 RW1S Offset: 94h Reset Value Description 0b Memory Calibration Done Used to Facilitate handshake between BIOS and Pcode Memory Calibration Done – DRAM power meter coeffs are now ready for sampling; DRAM PWR Mtr runs only with OLTT up until this bit is set. Once this bit is set, DRAM PWR MTR can start using the DRAM weights.
Processor Uncore Configuration Registers 4.4.3.7 MC_BIOS_REQ—MC_BIOS_REQ Register This register allows BIOS to request Memory Controller clock frequency. MC_BIOS_REQ Bus: 1 Bit Attr Reset Value 31:6 RV 0b 5:0 4.4.3.8 Device: 10 RWS 00h Function: 1 Offset: 98h Description Reserved Request Data These 6 bits are the data for the request. The only possible request type is MC frequency request. The encoding of this field is indicating the Dclk multiplier: Binary Dec Dclk Equation Dclk freq.
Processor Uncore Configuration Registers 4.4.3.9 SAPMCTL—System Agent Power Management Control Register PCODE will sample this register at the end of Phase 4. SAPMCTL Bus: 1 Function: 1 Offset: B0h Bit Attr Reset Value 31 RW-KL 0b Lock Indication When set to 1b this bit locks various PM registers. 0b SetVID Decay Disable This bit is used by BIOS to disable SETVID Decay to enable use of VR12 designs that do not support decay function.
Processor Uncore Configuration Registers SAPMCTL Bus: 1 Device: 10 Function: 1 Offset: B0h Bit Attr Reset Value Description 12 RW-L 1b Non-Snoop Wakeup Triggers Self Refresh Exit When this bit is set to 1b, a Non-Snoop wakeup signal from PCH sideband indication will cause the PCU to force the MC to exit from Self-Refresh. Otherwise, the Non-Snoop indication will not affect the Self Refresh exit policy.
Processor Uncore Configuration Registers 4.4.3.10 M_COMP—Memory COMP Control Register M_COMP Bus: 1 Function: 1 Offset: B8h Bit Attr Reset Value 31:9 RV 0h Reserved 8 RW1S 0b Force COMP Cycle Writing 1 to this field triggers a COMP cycle. HW will reset this bit when the COMP cycle ends. 7:5 RV 0h Reserved 4:1 RW-L Dh Periodic COMP Interval This field indicates the period of RCOMP. The time is indicated by power(2,COMP_INTERVAL) * 10.24 usec.
Processor Uncore Configuration Registers 4.4.3.12 RINGTIMERS—RING Timers Register RING Timers in 10n s granularity. RINGTIMERS Bus: 1 Function: 1 Offset: C4h Bit Attr Reset Value Description 31:22 RW-L 200h RCLK PLL SFR Timer This field is used to generate a deterministic time for SFR (5 uSec). The value is defined in BCLK granularity (10 ns units). The default value of 200h corresponds to 5.12 uSec.
Processor Uncore Configuration Registers 4.4.4 PCU2 Registers 4.4.4.1 CPU_BUS_NUMBER—CPU Bus Number Register This register is used by BIOS to write the Bus number for the socket. Pcode will use these values to determine whether PECI accesses are local or downstream. CPU_BUS_NUMBER Bus: 1 Device: 10 4.4.4.
Processor Uncore Configuration Registers DYNAMIC_PERF_POWER_CTL Bus: 1 Device: 10 4.4.4.
Processor Uncore Configuration Registers 4.4.4.5 GLOBAL_NID_MAP_REGISTER_0 Register This reister is in the PCU CR space. It contains NID information for all the sockets in the platform. BIOS should map the Master socket NID to the Socket0 entry. Expectation is that BIOS will write this register during the Reset/Init flow.
Processor Uncore Configuration Registers 4.4.4.6 PKG_CST_ENTRY_CRITERIA_MASK Register This register is used to configure which events will be used as a gate for PC3 entry. Expectation is that IOS will write this register based on the system config and devices in the system. It is expected that disabled Intel QPI/PCIe links must report L1. PKG_CST_ENTRY_CRITERIA_MASK Bus: 1 Device: 10 Function: 2 4.4.4.
Processor Uncore Configuration Registers 4.4.4.8 PACKAGE_RAPL_PERF_STATUS Register This register is used by Pcode to report Package Power limit violations in the Platform PBM. PACKAGE_RAPL_PERF_STATUS Bus: 1 Device: 10 Bit Attr Reset Value 63:32 RV 0h 31:0 4.4.4.
Processor Uncore Configuration Registers 4.4.4.10 DRAM_ENERGY_STATUS Register DRAM energy consumed by all the DIMMS in all the Channels. The counter will wrap around and continue counting when it reaches its limit. The energy status is reported in units which are defined in DRAM_POWER_INFO_UNIT_MSR[ENERGY_UNIT]. The data is updated by PCODE and is Read Only for all SW. DRAM_ENERGY_STATUS Bus: 1 Device: 10 4.4.4.
Processor Uncore Configuration Registers 4.4.4.12 DRAM_PLANE_POWER_LIMIT—DRAM Plane Power Limit Register This register is used by BIOS/OS/Integrated Graphics Driver/CPM Driver to limit the power budget of DRAM Plane. The overall package turbo power limitation is controlled by DRAM_PLANE_POWER_LIMIT.
Processor Uncore Configuration Registers 4.4.4.14 PERF_P_LIMIT_CONTROL Register This register is BIOS configurable. Dual mapping will prevent additional fast path events or polling needs from PCODE. Hardware does not use the CSR input, it is primarily used by PCODE. Note that PERF_P_LIMIT_CLIP must be nominally configured to guaranteed frequency + 1, if turbo related actions are needed in slave sockets.
Processor Uncore Configuration Registers 4.4.4.15 IO_BANDWIDTH_P_LIMIT_CONTROL Register This register provides various controls.
Processor Uncore Configuration Registers 4.4.4.16 MCA_ERR_SRC_LOG—MCA Error Source Log Register MCSourceLog is used by the PCU to log the error sources. This register is initialized to zeroes during reset. The PCU will set the relevant bits when the condition they represent appears. The PCU never clears the registers-the UBox or off-die entities should clear them when they are consumed, unless their processing involves taking down the platform. MCA_ERR_SRC_LOG Bus: 1 Device: 10 4.4.4.
Processor Uncore Configuration Registers 4.4.4.18 THERMTRIP_CONFIG—ThermTrip Configuration Register This register is used to configure whether the Thermtrip signal only carries the processor Trip information, or does it carry the Mem trip information as well. The register will be used by HW to enable ORing of the memtrip info into the thermtrip OR tree.
Processor Uncore Configuration Registers 4.4.5 PCU3 Registers 4.4.5.1 DEVHIDE[0:7]—Function 0 Device Hide Register This register is used by BIOS to hide functions in devices. DEVHIDE[0:7] Bus: 1 4.4.5.2 Device: 10 Function: 3 Offset: 40h, 44h, 48h, 4Ch, 50h, 54h, 58h, 5Ch Bit Attr Reset Value Description 31:0 RW-LB 000000 00h Disable Function A bit set in this register implies that the appropriate device function is not enabled.
Processor Uncore Configuration Registers 4.4.5.3 CAPID0 Register This register is a processor Capability Register used to expose to BIOS for SKU differentiation. CAPID0 Bus: 1 510 Device: 10 Function: 3 Bit Attr Reset Value 31 RO-FW 0b PCLMULQ_DIS Disable PCLMULQ instructions 30 RO-FW 0b DCU_MODE 0 = Normal 1 = 16K 1/2 size ECC mode 29 RO-FW 0b PECI_EN Enable PECI to the processor Offset: 84h Description 28 RO-FW 0b ART_DIS SparDisable support for Always Running APIC Timer.
Processor Uncore Configuration Registers CAPID0 Bus: 1 4.4.5.4 Device: 10 Bit Attr Reset Value 12 RO-FW 0b 11:9 RO-FW 000b 8 RO-FW 0b Function: 3 Offset: 84h Description HT_DIS Disable multi threading LLC_WAY_EN: Enable LLC ways Value Cache Size ’000 0.5 M (4 lower ways) ’001 1 M (8 lower ways) ’010 1.5 M (12 lower ways) ’011 2 M (16 lower ways) ’100 2.5M (20 lower ways) PRG_TDP_LIM_EN Allows usage of TURBO_POWER_LIMIT MSRs CACHESZ: Minimal LLC size/ways.
Processor Uncore Configuration Registers CAPID1 Bus: 1 Bit 29:26 512 Device: 10 Attr RO-FW Function: 3 Offset: 88h Reset Value 0000b Description DMFC This field controls which values may be written to the Memory Frequency Select field 6:4 of the Clocking Configuration registers (MCHBAR Offset C00h). Any attempt to write an unsupported value will be ignored. [3:3] =If set, over-clocking is supported and bits [2:0] are ignored. [2:0] =Maximum allowed memory frequency.
Processor Uncore Configuration Registers 4.4.5.5 CAPID2 Register This register is a processor Capability Register used to expose to BIOS for SKU differentiation. CAPID2 Bus: 1 Device: 10 Bit Attr Reset Value 31:30 RO-FW 00b Function: 3 Offset: 8Ch Description QPI_SPARE 29:25 RO-FW 0h QPI_ALLOWED_CFCLK_RATIO_DIS Allowed CFCLK ratio is 12, 11, 10, 9, 8 (default), 7; one bit is allocated for each supported ratio except 8, the default ratio. Intel QPI transfer rate = 8 * CFCLK.
Processor Uncore Configuration Registers 4.4.5.6 CAPID3 Register This register is a processor Capability Register used to expose to BIOS for SKU differentiation. CAPID3 Bus: 1 Bit Attr Reset Value 31:30 RO-FW 00b Function: 3 Offset: 90h Description MC_SPARE 29:24 RO-FW 0h MC2GD: MC2GDBit[5:4] Tx Pulse Width Control Bit[1:0].
Processor Uncore Configuration Registers CAPID3 Bus: 1 Function: 3 Offset: 90h Bit Attr Reset Value 12 RO-FW 0b DISABLE_3N: Fused 3N Disable Control When set, 3N mode under normal/IOSAV operation (excluding MRS) is disabled. The default value may change after reset de-assertion. 11 RO-FW 0b DISABLE_DIR DIR disable control. When set, directory is disabled. 10 RO-FW 0b DISABLE_ECC: ECC Disable Control When set, ECC is disabled.
Processor Uncore Configuration Registers 4.4.5.8 FLEX_RATIO—Flexible Ratio Register This ’flexible boot’ register is written by BIOS in order to modify the maximum nonturbo ratio on the next reset. FLEX_RATIO Bus: 1 4.4.5.9 Device: 10 Attr Reset Value 63:17 RV 0h Reserved 16 RWS 0b Flex Enable Flex Ratio Enabled 15:8 RWS 00h Flex Ratio Desired Flex ratio. 7:0 RWS 00h Over Clocking Extra Voltage Extra voltage to be used for Over Clocking. The voltage is defined in units of 1/256 Volts.
Processor Uncore Configuration Registers 4.5 Processor Utility Box (UBOX) Registers The Utility Box is the piece of the processor logic that deals with the non mainstream flows in the system. This includes transactions like the register accesses, interrupt flows, lock flows and events. In addition, the Utility Box houses co-ordination for the performance architecture, and also houses scratchpad and semaphore registers 4.5.
Processor Uncore Configuration Registers Table 4-25.
Processor Uncore Configuration Registers 4.5.2 Processor Utility Box (UBOX) Registers 4.5.2.1 CPUNODEID—Node ID Configuration Register This is the Node ID Configuration Register CPUNODEID Bus: 1 4.5.2.2 Device: 11 Function: 0 Offset: 40h Bit Attr Reset Value 31:16 RV 0h 15:13 RW-LB 000b Node Controller Node Id Node ID of the Node Controller. Set by the BIOS.
Processor Uncore Configuration Registers 4.5.2.3 IntControl—Interrupt Control Register Interrupt Configuration Register IntControl Bus: 1 Function: 0 Offset: 48h Bit Attr Reset Value 31:19 RV 0h Reserved 0b IA32 Logical Flat or Cluster Mode Override Enable 0 = IA32 Logical Flat or Cluster Mode bit is locked as Read only bit. 1 = IA32 Logical Flat or Cluster Mode bit may be written by SW, values written by xTPR update are ignored.
Processor Uncore Configuration Registers 4.5.2.4 LockControl—Lock Control Register LockControl Bus: 1 4.5.2.5 Device: 11 Function: 0 Bit Attr Reset Value 31:5 RV 0h Reserved 4 RW 0b Compatibility Mode Enable Compatibility Mode 3:1 RW 001b 0 RW 0b Offset: 50h Description Delay Between tTo Locks This may be used to prevent starvation on frequent Lock usage. 000 = 0h 001 = 200h (1.
Processor Uncore Configuration Registers 4.5.2.6 CoreCount—Number of Cores Register Reflection of the LTCount2 register CoreCount Bus: 1 4.5.2.
Processor Uncore Configuration Registers 4.5.2.
Processor Uncore Configuration Registers 4.5.3.3 LocalSemaphore[0:1]—Local Semaphore 0 Register unCore Semaphore register is a resource shared by all threads even though it has access and view for each one of the threads. Each one of the fields is identified to be a shared or a dedicated element.
Processor Uncore Configuration Registers 4.5.3.4 SystemSemaphore[0:1]—System Semaphore 0 Register unCore Semaphore register is a resource shared by all threads even though it has access and view for each one of the threads. Each one of the fields is identified to be a shared or a dedicated element.
Processor Uncore Configuration Registers 4.5.3.5 DEVHIDE[0:7]—Device Hide 0 Register Device Hide Register in CSR space DEVHIDE[0:7] Bus: 1 4.5.3.6 Device: 11 Function: 3 Offset: B0h, B4h, B8h, BCh, C0h, C4h, C8h, CCh Bit Attr Reset Value Description 31:0 RW-LB 000000 00h Disable Function: Disable Function(DisFn): A bit set in this register implies that the appropriate device function is not enabled.
Processor Uncore Configuration Registers 4.5.3.8 ABORTDEBUG1—Abort Debug Register Abort debug for aborting accesses ABORTDEBUG1 Bus: 1 4.5.3.9 Device: 11 Bit Attr Reset Value 31:0 RO FFFFFFFFh Function: 3 Offset: E0h Description Data Field Reset Value value for reads. Writes will be dropped.
Processor Uncore Configuration Registers 4.6 Performance Monitoring (PMON) Registers 4.6.1 CSR Register Maps The following register maps are for performance monitoring: Table 4-26.
Processor Uncore Configuration Registers 4.6.2 Processor Performance Monitor Registers 4.6.2.1 PmonCtr[0:4]—PMON Counter PmonCtr Bus: 1 Bus: 1 Bus: 1 Bus: 1 Bus: 1 4.6.2.
Processor Uncore Configuration Registers 4.6.2.
Processor Uncore Configuration Registers PmonCntrCfg Bus: 1 Bus: 1 Bus: 1 Bus: 1 Bus: 1 Bit 16 4.6.2.
Processor Uncore Configuration Registers PmonUnitCtrll Bus: 1 Bus: 1 Bus: 1 Bus: 1 Bus: 1 4.6.2.6 Device: Device: Device: Device: Device: 8 9 14 16 19 Function: Function: Function: Function: Function: 2 Offset: 2 Offset: 1 Offset: 0, 1,4,5 Offset: 1 Offset: F4h F4h F4h F4h F4h Bit Attr Reset Value Description 0 WO 0h Reset Counter Configs When this bit is written to, the counter configuration registers will be reset. This does not effect the values in the counters.
Processor Uncore Configuration Registers 4.6.2.7 HaPerfmonAddrMatch0— Home Agent Perfmon Address Match Register 0 These registers are used to dump the contents of the home agent tracker contents and control states. HaPerfmonAddrMatch0 Bus: 1 Device: 14 4.6.2.8 Bit Attr Reset Value 31:6 RWS 000000 0h 5:0 RV 00h Function: 1 Offset: 40h Description Low Physical Address of a cache line This field contains 26 bits of low physical address 31:6 of a cache line.
Processor Uncore Configuration Registers 4.6.2.10 HAPmonDbgCtrl—HA Perfmon Debug Control Register Control register for the special debug wrapper around counter 4 in the Home Agent. HAPmonDbgCtrl Bus: 1 4.6.2.11 Device: 14 Bit Attr Reset Value 31:14 RV 0h Reserved Function: 1 Offset: 4Ch Description 13 RW-L 0b ClockedIncEnable Changes when the counter increments. Rather than incrementing based on the event, the counter will increment by 1 in each cycle.
Processor Uncore Configuration Registers 4.7 R2PCIe Routing Table and Ring Credits 4.7.1 R2PCIe Routing Register Map Table 4-27.
Processor Uncore Configuration Registers 4.7.1.1 IIO_BW_COUNTER—IIO Bandwidth Counter Register IIO_BW_COUNTER Bus: 1 Device: 19 Bit Attr Reset Value 31:30 RV 0h 29:0 4.7.1.2 RW1C Description Reserved IIO Bandwidth Counter Free running counter that increments on each AD request sent to the ring. Pcode uses this for power metering and also for uncore P state related decisions. Pcode can clear this counter by writing a 1 to all bits in this field, at which time the counter starts from 0.
Processor Uncore Configuration Registers 4.7.1.4 R2PINGERRMSK0 Register R2PINGERRMSK0 Bus: 1 Device: 19 Bit 4.7.1.
Processor Uncore Configuration Registers 4.7.1.
Processor Uncore Configuration Registers 4.7.1.
Processor Uncore Configuration Registers 4.7.1.
Processor Uncore Configuration Registers 4.7.1.10 R2PCIE_DBG_BUS_CONTROL Register R2PCIE_DBG_BUS_CONTROL Bus: 1 Device: 19 Attr Reset Value 7:5 RV 0h Reserved 4 RWS-L 0b invert_match_result 3 RWS-L 1b debugbus_match_and_or 2 RWS-L 0b debugbus_enable_gdxc 1:0 RWS-L 00b Bit 4.7.1.
Processor Uncore Configuration Registers 4.7.1.14 R2PCIE_ASC_LDVAL Register R2PCIE_ASC_LDVAL Bus: 1 Device: 19 4.7.1.
Processor Uncore Configuration Registers 4.8 MISC Registers 4.8.1 DDRIOTrainingModeA[0:1]—DDRIOTrainingMode Register DDRIOTrainingModeA[0:1] Bus: 1 Device: 17 Bus: 1 Device: 15 Function: 0 Function: 6 Offset: 108h Offset: 108h Bit Attr Reset Value 31:23 RV 0h Reserved 22 RW-LB 0b DDRIOX4X8 Dynamic X4/X8 mode 21 RW-LB 0h DDRIORDIMMEn Tdqs enable, when enabled, in tdqs mode.
Processor Uncore Configuration Registers DDRIOTrainingModeA[0:1] Bus: 1 Device: 17 Bus: 1 Device: 15 Bit 4.8.2 Attr Description 1 RW-LB 0b DDRIOWriteLevelingTrainEnable Write Leveling training mode enable. In this mode a programmable # of DQS pulses are issued according to EnableDqsWL setup. The DDR (which should also be in WR-leveling mode) samples CLK with DQS rising edge and drives it on one of the DQ pins. In this mode only WR command sends strobe.
Processor Uncore Configuration Registers 4.8.4 DDRIOBuffCfgA[0:1]—DDRIOBuffCfg Register DDRIOBuffCfgA[0:1] Bus: 1 Device: 17 Bus: 1 Device: 15 Bit Attr Reset Value 31 RW-LB 0b Function: 0 Function: 6 Offset: 118h Offset: 118h Description DDRIOBusAnchorEn Enables the ODT 1 to 2 qclk ahead of a write operation. DDRIOVrefSel Selects the Vref voltage value coming out of internal Vref generator Vrefset[5:0] Vref (mv) Vrefset[5:0] Vref (mv) 000000 750.00 100000 750.00 000001 742.19 100001 757.
Processor Uncore Configuration Registers 4.8.5 DDRIOTXRXBotRank0A[0:1]— DDRIOTXRXBotRank0 Register DDRIOTXRXBotRank0A[0:1] Bus: 1 Device: 17 Bus: 1 Device: 15 546 Function: 0 Function: 6 Offset: 120h Offset: 120h Bit Attr Reset Value Description 31 RW-LB 0b DDRIOTxDqDelayCycleN1 Determines the cycle delay between DQ and DQS before applying the PI settings. Need to be used when DQS PI is bigger the DQ PI setting.
Processor Uncore Configuration Registers 4.8.6 DDRIORXTopRank0A[0:1]—DDRIORXTopRank0 Register DDRIORXTopRank0A[0:1] Bus: 1 Device: 17 Bus: 1 Device: 15 Offset: 140h Offset: 140h Bit Attr Reset Value 31:30 RV 0h Reserved 29:24 RW-LB 0h DDRIORxRcvEnCodingN1 Defines the number of steps to delay ReceiveEnable (0-63), per rank setting.
Processor Uncore Configuration Registers 4.8.8 DDRIOCtlPICode0A[0:1]—DDRIOCtlPICode0 Register DDRIOCtlPICode0A[0:1] Bus: 1 Device: 17 Bus: 1 Device: 15 Offset: 310h Offset: 310h Bit Attr Reset Value 31 RV 0b Reserved 30 RW-LB 1b DDRIO0CtlXoverEnable3: Xover Enable for PI Group 3 When set, the phase interpolator is used. When cleared, the phase interpolator is bypassed and delay is shorter than PI setting 0 due to PI intrinsic delay.
Processor Uncore Configuration Registers 4.8.9 DDRIOCtlPICode1A[0:1]—DDRIOCtlPICode1 Register DDRIOCtlPICode1A[0:1] Bus: 1 Device: 17 Bus: 1 Device: 15 Function: 0 Function: 6 Offset: 314h Offset: 314h Bit Attr Reset Value 31:23 RV 0b Reserved 22 RW-LB 1b DDRIO1CtlXoverEnable6: Xover Enable for CTL PI Group 6 When set, the phase interpolator is used.
Processor Uncore Configuration Registers 4.8.10 DDRIOLogicDelayA[0:1]—DDRIOLogicDelay Register Logic delay control register. When set, the corresponding PI group is delayed by one qclk. The LogicDelay register settings are additive delays to either the PhaseDelay setting or the CMD/CTL PI settings, depending on the CmdXoverEnable setting. DDRIOLogicDelayA[0:1] Bus: 1 Device: 17 Bus: 1 Device: 15 Bit 4.8.
Processor Uncore Configuration Registers 4.8.12 DDRIOCmdPICodeA[0:1]—DDRIOCmdPICode Register DDRIOCmdPICodeA[0:1] Bus: 1 Device: 17 Bus: 1 Device: 15 Function: 0 Function: 6 Offset: 30Ch Offset: 30Ch Bit Attr Reset Value 31 RV 0b Reserved 30 RW-LB 1b DDRIOCmdXoverEnable3: Xover Enable for PI Group 3 When set, the phase interpolator is used. When cleared, the phase interpolator is bypassed and delay is shorter than PI setting 0 due to PI intrinsic delay.
Processor Uncore Configuration Registers 4.8.
Processor Uncore Configuration Registers 4.8.
Processor Uncore Configuration Registers 4.8.
Processor Uncore Configuration Registers 4.8.16 DDRIOCkLogicDelayA[0:1]—DDRIOCkLogicDelay Register Logic delay of 1 QCLK in CLK slice DDRIOCkLogicDelayA[0:1] Bus: 1 Device: 17 Bus: 1 Device: 15 Bit Attr Reset Value 7:6 RV 0 5:4 RW-LB 00b 3:2 RV 0 1:0 4.8.17 RW-LB 00b Function: 0 Function: 6 Offset: 398h Offset: 398h Description Reserved DDRIOCKAlignLogicDelay1 Shifts Clock by one qclk.
Processor Uncore Configuration Registers DDRIOCompOvrOfst2A[0:1] Bus: 1 Device: 17 Bus: 1 Device: 15 4.8.
Processor Uncore Configuration Registers 4.8.19 DDRIOCompCfgSPDA[0:1] Register Note: Only channel 1 or channel 3 are connected to the SPD buffers. Programming the A0 (channel 0 or channel2) has no effect. SPD Comp Config and LVDDR enable, statically configured by BIOS and this is not part of the period RCOMP.
Processor Uncore Configuration Registers 4.8.20 QPIREUT_PM_R0—REUT Power Management Register 0 QPIREUT_PM_R0 Bus: 1 Device: 8 Bus: 1 Device: 9 558 Function: 3 Function: 3 Reset Value Bit Attr 31:28 RWS-LV 0b TL0sDriveRemote 27:26 RV 0b Reserved Offset: 190h Offset: 190h Description 25:24 RWS-LV 0b TL0sSleepMinRemote: TL0S_SLEEP_MIN_REMOTE If # of links supported is greater than 0 then, Link Select must always be used to display the current read value for this field.
Processor Uncore Configuration Registers QPIREUT_PM_R0 Bus: 1 Device: 8 Bus: 1 Device: 9 Bit Attr Function: 3 Function: 3 Offset: 190h Offset: 190h Reset Value Description TL0sWakeRemote: TL0S_WAKE_REMOTE Link Select must always be used to display the current read value for this field. There is a write dependency for this field based on the value of Can Control Multiple Links? If Can Control Multiple Links? = 0, then Link Select must be used to only write to the selected Link.
Processor Uncore Configuration Registers QPIREUT_PM_R0 Bus: 1 Device: 8 Bus: 1 Device: 9 Bit 5:0 4.8.21 Attr RWS-L Offset: 190h Offset: 190h Reset Value Description 12h TL0sWake: TL0S_WAKE If # of links supported is greater than 0, then Link Select must always be used to display the current read value for this field.
Processor Uncore Configuration Registers 4.8.22 TXEQ_LVL0_0 Register TXEQ_LVL0_0 Bus: 1 4.8.23 Function: 4 Offset: 7E4h Bit Attr Reset Value 31:30 RV 0h Reserved 29:24 RWS-L 3Fh bndl4 Transmit Equalization Level0 coefficients for FIR settings 23:18 RWS-L 3Fh bndl3 Description 17:12 RWS-L 3Fh bndl2 11:6 RWS-L 3Fh bndl1 5:0 RWS-L 3Fh bndl0 TXEQ_LVL0_1 Register TXEQ_LVL0_1 Bus: 1 4.8.
Processor Uncore Configuration Registers 4.8.25 TXEQ_LVL1_1 Register TXEQ_LVL1_1 Bus: 1 4.8.
Processor Uncore Configuration Registers 4.8.28 TXEQ_LVL3_0 Register TXEQ_LVL3_0 Bus: 1 4.8.
Processor Uncore Configuration Registers 564 Datasheet, Volume 2