User Guide

ManualsBrandsIntel ManualsGeneral Flowintel 1.5.1. Nios II Booting General Flow

Generic Nios II Booting Methods User Guide

2016.05.24

UG-20001

Send Feedback

Overview

Altera

Nios

II processor is a so processor that supports all Altera System on Chip (SoC) and Field

Programmable Gate Array (FPGA) families. Developing Nios II embedded programs can be based on

Altera hardware abstraction layer (HAL). e creation and management of soware projects based on the

HAL is integrated tightly with the Nios II Soware Build Tools (SBT).

e boot memory could be the Compact Flash Interface (CFI) ash, User Flash Memory (UFM) ash,

Altera Serial Flash (EPCS)/Altera Quad Serial Flash (EPCQ) conguration device or on-chip RAM

(OCRAM). Regardless of the nature of the boot memory, HAL-based systems are constructed so that the

reset vector and all program and data sections are initially stored in the boot memory. e HAL provides a

small boot loader program (also known as boot copier) that copies these sections to their run time

location at boot time. You can specify the run time locations for program and data memory by

manipulating the Nios II BSP settings.

is document describes:

• e Nios II processor boot copier that boots your Nios II system according to the boot memory

selection

• Nios II processor booting options and general ow

• Nios II programming solutions for selected boot memory

Prerequisites

You are required to have knowledge in instantiating and developing a system with a Nios II processor.

Altera recommends that you go through the following online tutorials and training materials before using

this application note:

• Nios II Classic Soware Developer’s Handbook

• Nios II Flash Programmer User Guide

• AN736: Nios II Processor Booting from Altera Serial Flash (EPCQ)

• AN730: Nios II Processor Booting Methods in MAX 10 Devices

• AN370: Using the Serial Flash Loader with the Quartus Prime Soware

• Parallel Flash Loader IP Core User Guide

• AN458: Alternative Nios II Boot Methods

Related Information

•

Nios II Classic Soware Developer's Handbook

Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current

specications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.

Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly

agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specications before relying on any published information

and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

ISO

9001:2015

Registered

www.altera.com

101 Innovation Drive, San Jose, CA 95134

Summary of content (15 pages)

PAGE 1
Generic Nios II Booting Methods User Guide 2016.05.24 UG-20001 Subscribe Send Feedback Overview Altera® Nios® II processor is a soft processor that supports all Altera System on Chip (SoC) and Field Programmable Gate Array (FPGA) families. Developing Nios II embedded programs can be based on Altera hardware abstraction layer (HAL). The creation and management of software projects based on the HAL is integrated tightly with the Nios II Software Build Tools (SBT).
PAGE 2
UG-20001 2016.05.
PAGE 3
UG-20001 2016.05.24 Memcpy-Based Boot Copier 3 You may enable the alt_load() function in the HAL code. This function operates as a mini boot copier that copies only the writable memory sections to RAM based on the BSP settings. It optionally copies sections from the boot memory to RAM. It can copy data sections (.rodata, .rwdata, .exceptions) to RAM but not the code sections (.text). The code section (.text) section is a read-only section and remains in the booting flash memory region.
PAGE 4
UG-20001 2016.05.24 Memcpy-Based Boot Copier Figure 1: Memory Map for EPCQ and CFI Flash with Memcpy-based Bootcopier Note: At the start of the memory map is the FPGA image, followed by the customer data which consists of boot copier and application code. The size of the FPGA image is unknown and the exact size can only be known after the Quartus Prime project compilation.
PAGE 5
UG-20001 2016.05.24 EPCS Controller-Based Boot Copier 5 Figure 2: Memory Map of a System Using UFM with memcpy-based Boot Copier The memcpy-based boot copier is automatically incorporated as part of the: • HEX file during memory initialization file generation ("mem_init_generate" target) in the Quartus Prime Programming Flow method • SREC image (*.
PAGE 6
UG-20001 2016.05.24 Nios II Processor Booting Methods Figure 3: Memory Map for EPCS Flash with EPCS Controller-based Bootcopier Note: Quartus Prime and Nios II Flash programming flow is briefly described in the Nios II Booting General Flow diagram. Related Information Nios II Booting General Flow on page 8 Nios II Processor Booting Methods There are a few methods to boot up Nios II processor in Altera devices. The methods to boot up Nios II processor varies according to the flash memory selection.
PAGE 7
UG-20001 2016.05.
PAGE 8
UG-20001 2016.05.24 Nios II Booting General Flow Nios II Booting General Flow Design • Create your Nios II processor-based project using the Quartus Prime software and Qsys. Configuration and Compilation • Set the Nios II processor reset and exception vector based on your boot options. • Generate your design in Qsys. • Compile your design in the Quartus Prime software. BSP Editor Settings • Use Nios II SBT, create the Nios II processor HAL BSP based on the .
PAGE 9
UG-20001 2016.05.
PAGE 10
UG-20001 2016.05.24 Summary of Nios II Processor Vector Configurations and BSP Settings Boot Option BSP Settings: Settings.Advanced.hal.linker BSP Editor Setting: Linker Script enable the following settings in Settings.Advanced.hal.linker: • allow_code_at_reset • enable_alt_load • enable_alt_load_copy_ rodata • enable_alt_load_copy_ rwdata Nios II processor applica‐ tion copied from CFI flash to RAM using boot copier All settings in Settings.Advanced.hal.linker are left unchecked.
PAGE 11
UG-20001 2016.05.24 Nios II Processor Application Execute-In-Place from CFI Flash Boot Option Nios II processor applica‐ tion execute-in-place from Altera On-chip Memory (OCRAM) BSP Settings: Settings.Advanced.hal.linker Enable allow_code_at_reset in Settings.Advanced.hal.linker and leave the other settings unchecked.
PAGE 12
UG-20001 2016.05.24 Nios II Processor Application Copied from EPCS Flash to RAM Using Boot Copier Nios II Processor Application Copied from EPCS Flash to RAM Using Boot Copier The EPCS address space is not mapped into the Altera Avalon EPCS Flash Controller’s Avalon MM slave interface. Instead, read or write accesses are done through CSRs. Upon system reset, the EPCS device needs to be initialized before usage.
PAGE 13
UG-20001 2016.05.24 Elf2flash Utility 13 Elf2flash Utility The elf2flash utility generates SREC image (*.flash extension) by extracting ELF loadable sections. The SREC image can then be programmed into flash devices supported by Nios II Flash Programmer. For CFI flash devices, both the optional CFI bootcopier and ELF loadable sections are stored in the device. When the CFI bootcopier is not used, the SREC image only contains loadable section data.
PAGE 14
UG-20001 2016.05.
PAGE 15
Document Revision History for Generic Nios II Booting Methods 2016.05.24 UG-20001 Subscribe Date Send Feedback Version Changes May 2016 2016.05.24 • Renamed Quartus II to Quartus Prime. • Updated the "Summary of Nios II Processor Vector Configurations and BSP Settings" section so that it will be in alignment with AN730. September 2015 2015.09.11 Removed the Nios II processor boot methods list. June 2015 2015.06.29 Initial Draft Intel Corporation. All rights reserved.