User's Manual
Table Of Contents
- 1.0 General Device Overview
- 2.0 Basic Operating Information
- 3.0 eUniStone Interfaces
- 4.0 General Device Capabilities
- 5.0 Bluetooth Capabilities
- 6.0 Electrical Characteristics
- 7.0 Package Information
- 8.0 Bluetooth Qualification and Regulatory Certification
- 8.1 Reference Design
- 8.2 FCC Class B Digital Devices Regulatory Notice
- 8.3 FCC Wireless Notice
- 8.4 FCC Interference Statement
- 8.5 FCC Identifier
- 8.6 European R&TTE Declaration of Conformity
- 8.7 Bluetooth Qualified Design ID
- 8.8 Industry Canada Certification
- 8.9 Label Design of the Host Product
- 8.10 Regulatory Test House
- 9.0 Assembly Guidelines
- References
- Terminology
eUniStone
PBA 31309
General Device Overview
User’s Manual Intel Public 14
Hardware Description Revision 1.0, 1-Feb-2013
The UART interface is used for communication between the host and eUniStone. The
lines UARTTXD and UARTRXD are used for commands, events and data. The lines
UARTRTS and UARTCTS are used for hardware flow control.
Low power mode control of eUniStone and the host can be implemented in by using the
pins P0.14 and P0.0. P0.14 is used by the host to allow eUniStone to enter low power
mode and P0.0 is used by eUniStone to wake-up the host when attention is required. To
save current in idle mode, the host could hardware reset the module using the RESET#.
Power is supplied to a single VSUPPLY input from which internal regulators can generate
all required voltages. The UART and the GPIO’s interfaces have separate supply
voltages so that they can comply with host signaling.
1.6 SW Patch in EEPROM
Bugfixes for the SW in ROM are downloaded from the EEPROM. Intel may include new
bugfixes in EEPROM during product lifetime..