T E C H N I C A L D ATA S H E E T Integral Z Series PATA 2.5 Inch Specification Version 1.
Features: Standard 50pin 2.
TABLE OF CONTENTS 1.0 BLOCK DIAGRAM ................................................................................................................................ ..4 1.1 CAPACITY SPECIFICATION ............................................................................................................... 4 2.0 SPECIFICATION ............................................................................................................ 4 2.1 PIN ASSIGNMENTS ................................................
1.0 Block Diagram 1.1 Capacity Specification Density Total Bytes 32GB 31,272,321,024 62,545,158,144 127,909,232,640 64GB 128GB Cylinders 16383 16383 16383 Heads Sectors 16 16 16 63 61,078,752 63 122,158,512 63 249,822,720 2.0 Specification 2.
31 INTRQ 32 IOIS16 33 DA1 34 -PDIAG:-CBLID 35 DA0 36 DA2 37 -CS0 38 -CS1 39 -DASP 40 GND 41 VCC 42 VCC 43 GND 44 NC 2.2 Pin Description Pin No. Signal I/O* Description 01 -RESET I Hardware reset signal from the host 17,15,13,11,09,07, DD0~DD15(Device 05,03,04,06,08,10, Data) I/O DD(7:0) are used for 8-bit 12,14,16,18 21 16-bit bi-direction Data Bus. register transfers. DMARQ(DMA Request) O For DMA data transfers.
25 IORDY(I/O channel O ready) This signal is used to temporarily stop the host register access (read or write) when the device is not ready to respond to a data transfer request. DDMARDY(UDMA The device will assert this ready) signal to indicate that the device is ready to receive UDMA data-out burst. DSTROBE(UDMA data When UDMA mode DMA Read strobe) is active, this signal is the data-in strobe generated by the device.
-CBLID(Cable assembly type identify) 37, 38 -CS0, -CS1(Chip select) I These signals are used to select the Command Block and Control Block registers. When –DMACK is asserted, -Cs0 and –Cs1 shall be negated and transfers shall be 16-bit wide. 39 -DASP(Device active, I/O During the reset protocol, -DASP Device 1 present) shall be asserted by Device 1 to indicate that the device is present. 41, 42 VCC P Power supply 02, 19, 22, 24, GND -- Ground.
3.2 DC Characteristics of 5.0V I/O Cells(Host Interface) Symbol Parameter Conditions Vil Input Low Voltage TTL(5V) Vih Input High Voltage Vil Input Low Voltage Vih Input High Voltage Vol Output Low Voltage TTL(3.3V) |Iol| = 4~32 MIN TYP MAX Unit -- -- 0.85 V 1.25 -- -- V -- -- 1.05 V 1.75 -- -- V -- -- 0.4 V 2.
3.3 AC Characteristics 3.3.
PIO timing parameters t0 Cycle time Mode Mode Mode Mode Mode Not 0 ns 1 ns 2 ns 3 ns 4 ns e 600 383 240 180 120 1,4 70 50 30 30 25 165 125 100 80 70 1 -- -- -- 70 25 1 60 45 30 30 20 30 20 15 10 10 50 35 20 20 20 5 5 5 5 5 30 30 30 30 30 2 20 15 10 10 10 10 0 0 0 0 0 (min) t1 Address valid to DIOR-/DIOW- setup (min) t2 DIOR-/DIOW(min) t2i DIOR-/DIOW- recovery time (min) t3 DIOW- data setup (min) t4 DIOW- data hold (min) t5
3. The delay from the activation of FIOR- or DIOW- until the state of IORDY is first sampled. If IORDY is inactive then the host shall wait until IORDY is active before the PIO cycle is complete. If the device is not driving IORDY negated at the tA after the activation of DIOR- or DIOW-, that t5 shall be met and tRD is not applicable. If the device is driving IORDY negated at the time tA after the activation of DIOR- or DIOW-, then tRD shall be met and t5 is not applicable. 4.
(Sustaining a Multiword DMA data burst) (Device terminating a Multiword DMA data burst) 12
(Host terminating a Multiword DMA data burst) 13
Multiword DMA timing parameters t0 Cycle time Mode Mode Mode 0 ns 1 ns 2 ns 480 150 120 (min) tD See note DIOR-/DIOW- asserted pulse width 215 80 70 (min) tE Note See note DIOR- data access 150 60 50 5 5 5 100 30 20 20 15 10 0 0 0 20 5 5 50 50 25 (max) tF DIOR- data hold (min) tG DIOR-/DIOW- data setup (min) tH DIOW- data hold (min) tI DMACK to DIOR-/DIOW- setup (min) tJ DIOR-/DIOW- to DMACK hold (min) tKR DIOR- negated pulse width (min) tKW DIOW- negat
3.3.
Ultra DMA data burst timing descriptions 16
(Initialing an Ultra DMA data-in burst) (Sustained Ultra DMA data-in burst) 17
(Device terminating an Ultra DMA data-in burst) (Host terminating an Ultra DMA data-in burst) 18
(Initialing an Ultra DMA data-out data burst) (Sustained Ultra DMA data-out burst) 19
(Host terminating an Ultra DMA data-out burst) (Device terminating an Ultra DMA data-out burst) 20
3.4 Power Management System Power Consumption: (Ta = 0 to 700C) Symbol Parameter Conditions MIN TYP MAX Unit Iccr Read current 5V - 130 - mA Iccw Write current 5V - 140 - mA Ipd Power down current 5V - 0.2 0.4 mA Iccr Read current 3.3V - 200 - mA Iccw Write current 3.3V - 210 - mA Ipd Power down current 3.3V - 0.3 - mA 4.0 Software Interface 4.
4.2 Command Sets Below table summarizes the PATA 2.5” SSD command set with the paragraphs that follow describing the individual commands and task file for each command. No.
4.3 Identify Drive Information The Identity Drive Command enables Host to receive parameter information from the device. The parameter words in the buffer have the arrangement and meanings defined in below table. All reserve bits or words are zero.
Word Default Address Value 57-58 xxxxh 4 59 0101h 2 60-61 xxxxh 4 62 0000h 2 63 0007h 2 64 0003h 2 65 0078h 2 66 0078h 2 67 0078h 2 68 0078h 2 69-79 0000h 26 80 0030h Major version number 81 0000h Reserved 82 7009h 2 Supports Security Mode feature set 83 5004h 2 Reserved 84 4000h 85 7009h Feature Setting 86 1004h Feature Setting 87 4000h Feature Setting 88 203Fh 2 89-92 0000h 8 Reserved 93 xxxxh 94-128 0000h 2 Enhanced security erase
5.0 Physical Dimension 5.1 2.
