Datasheet

Data Sheet 2 Rev. 1.0, 2012-06-15
TLF80511
General Product Characteristics
4.2 Functional Range
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3 Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
4.2.1 Input Voltage Range for Normal
Operation
V
I
V
Q,nom
+ V
dr
40 V –
4.2.2 Extended Input Voltage Range
V
I,ext
3.3 40 V –
1)
1) Between min. value and V
Q,nom
+ V
dr
: V
Q
= V
I
- V
dr
. Below min. value: V
Q
= 0 V
4.2.3 Output Capacitor’s Requirements
for Stability
C
Q
1–µF–
2)
2) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%
ESR(C
Q
) –5Ω –
3)
3) relevant ESR value at f = 10 kHz
4.2.4 Junction Temperature T
j
-40 150 °C–
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Package Versions PG-TO263-3
4.3.1 Junction to Case
1)
1) Not subject to production test, specified by design
R
thJC
–4–K/W–
4.3.2 Junction to Ambient
1)
R
thJA
–22–K/W
2)
2) Specified R
thJA
value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
4.3.3 – 65 – K/W footprint only
3)
3) Specified R
thJA
value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm
3
board with 1 copper layer (1 x 70µm Cu).
4.3.4 – 39 – K/W 300 mm
2
heatsink
area on PCB
3)
4.3.5 – 33 – K/W 600 mm
2
heatsink
area on PCB
3)